1. Shifters Discussion D7.1 Example 18

2. 4-Bit Shifter

4. - Example 18: 4-bit shifter library IEEE; use IEEE.STD_LOGIC_1164.all; entity shift4 is port( d : in STD_LOGIC_VECTOR(3 downto 0); s : in STD_LOGIC_VECTOR(2 downto 0); y : out STD_LOGIC_VECTOR(3 downto 0) ); end shift4;

5. architecture shift4 of shift4 is begin process(d,s) begin case s is when "000" => y <= d;-- no shift when "001" => y <= '0' & d(3 downto 1);-- shr when "010" => y <= d(2 downto 0) & '0';-- shl when "011" => y <= d(0) & d(3 downto 1);-- ror when "100" => y <= d(2 downto 0) & d(3);-- rol when "101" => y <= d(3) & d(3 downto 1);-- asr when "110" => y <= d(1 downto 0) & d(3 downto 2);-- ror2 when "111" => y <= d;-- no shift when others => y <= d;-- no shift end case; end process; end shift4;

6. Aldec Active-HDL Simulation

7. y <= SHR(d,shift_count); y <= SHL(d,shift_count); shifts d right shift_count bits shifts d left shift_count bits

8. -- 16-bit shifter library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity shifter is port( d : in STD_LOGIC_VECTOR(15 downto 0); lr : in STD_LOGIC; shift_count : in STD_LOGIC_VECTOR(7 downto 0); y : out STD_LOGIC_VECTOR(15 downto 0) ); end shifter;

9. architecture shifter of shifter is begin process(d,lr,shift_count) begin if lr = '1' then y <= SHR(d,shift_count); else y <= SHL(d,shift_count); end if; end process; end shifter;