1. Edge-Triggered D Flip-Flops
Discussion 10.2
Example 26

2. Edge-Triggered D Flip-Flop

3. // Example 26a: Edge-triggered D flip-flop
module flipflop(
input wire clk,
input wire D,
output q,
output notq );
wire f1,f2,f3,f4,f5,f6;
assign #5 f1 = ~(f4 & f2);
assign #5 f2 = ~(f1 & f5);
assign #5 f3 = ~(f6 & f4);
assign #5 f4 = ~(f3 & clk);
assign #5 f5 = ~(f4 & clk & f6);
assign #5 f6 = ~(f5 & D);
assign q = f1;
assign notq = f2;
endmodule

4. Aldec Active-HDL Simulation

5. Edge-Triggered D Flip-Flop with set and clear

6. // Example 26b: D flip-flop with clr and set
module flipflopcs(
input wire clk,
input wire D,
input wire set,
input wire clr,
output q,
output notq );
wire f1,f2,f3,f4,f5,f6;
assign #5 f1 = ~(f4 & f2 & ~set);
assign #5 f2 = ~(f1 & f5 & ~clr);
assign #5 f3 = ~(f6 & f4 & ~set);
assign #5 f4 = ~(f3 & clk & ~clr);
assign #5 f5 = ~(f4 & clk & f6 & ~set);
assign #5 f6 = ~(f5 & D & ~clr);
assign q = f1;
assign notq = f2;
endmodule

7. Aldec Active-HDL Simulation