1. Divider
Discussion D7.3
Example 20

2. Division 10
1010
13 135 13 05
1101
00111
0000
01111
00101
0101

3. Division 8-bit/4-bit = 4:4
1010
1101
00111
0000
01111
00101
0101

4. Division 8-bit/4-bit = 4:4
1. Store the numerator in the concatenation of n1:n2
2. Store the denominator in d
3. Repeat 4 times:
Shift n1:n2 left one bit
If n1 > d
n1 = n1 – d;
n2[0] = 1;
4. quot = n2;
rem = n1[3:0];

5. div4a.vhd Combinational divide -- Example 20a: 4-bit divider
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity div4a is
port(
numer : in STD_LOGIC_VECTOR(7 downto 0);
denom : in STD_LOGIC_VECTOR(3 downto 0);
quotient : out STD_LOGIC_VECTOR(3 downto 0);
remainder : out STD_LOGIC_VECTOR(3 downto 0) );
end div4a;

6. architecture div4a of div4a is
begin
process(numer,denom)
variable d,n1: STD_LOGIC_VECTOR(4 downto 0);
variable n2: STD_LOGIC_VECTOR(3 downto 0);
d := '0' & denom;
n2 := numer(3 downto 0);
n1 := '0' & numer(7 downto 4);
for i in 0 to 3 loop
n1 := n1(3 downto 0) & n2(3);
n2 := n2(2 downto 0) & '0';
if n1 >= d then
n1 := n1 - d;
n2(0) := '1';
end if;
end loop;
quotient <= n2;
remainder <= n1(3 downto 0);
end process;
end div4a;

7. Divide Simulation

8. div synthesized circuit
denom(3:0)
remain(3:0)
quot(3:0)
numer(7:3)
numer(2:0)

9. Top-level Design