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March 8, 2006“Bus Stuttering”1 Bus Stuttering : An Encoding Technique To Reduce Inductive Noise In Off-Chip Data Transmission DATE 2006 Session 5B: Timing.

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Presentation on theme: "March 8, 2006“Bus Stuttering”1 Bus Stuttering : An Encoding Technique To Reduce Inductive Noise In Off-Chip Data Transmission DATE 2006 Session 5B: Timing."— Presentation transcript:

1 March 8, 2006“Bus Stuttering”1 Bus Stuttering : An Encoding Technique To Reduce Inductive Noise In Off-Chip Data Transmission DATE 2006 Session 5B: Timing and Noise Analysis Presenter:Ganesh Venkataraman Texas A&M University Authors: Brock J. LaMeres Agilent Technologies Sunil P. Khatri Texas A&M University Contact: sunilkhatri@tamu.edu

2 March 8, 2006“Bus Stuttering”2 Agenda Problem Motivation Our Solution Experimental Results

3 March 8, 2006“Bus Stuttering”3 Why is IC Packaging Important? All Electronic Circuitry Resides in a Package - The package serves many purposes: 1) Protection of devices 2) Density Translation 3) Thermal Dissipation 4) Manufacturing Standardization Packaging Limits System Performance

4 March 8, 2006“Bus Stuttering”4 Why is packaging limiting performance? IC Design/Fabrication is Outpacing Package Technology - We’re seeing exponential increase in IC transistor performance - >1.3 Billion transistors on 1 die [Fall IDF-05]

5 March 8, 2006“Bus Stuttering”5 Why is packaging limiting performance? Packages Have Been Designed for Mechanical Performance - Electrical performance was not primary consideration - IC’s limited electrical performance - Package performance was not the bottleneck

6 March 8, 2006“Bus Stuttering”6 Why is packaging limiting performance? VLSI Performance Exceeds Package Performance - Packages optimized for mechanical reliability, but still used due to cost - IC performance far exceeds package performance On-Chip - f IC > 4GHz - large signal counts - exponential scaling Package - f pkg < 2GHz - limited signal counts - linear scaling

7 March 8, 2006“Bus Stuttering”7 Why is packaging limiting performance? Package Interconnect Contains Parasitic Inductance - Long interconnect paths - Large return current loops Wire Bond Inductance (up to 10s of nH)

8 March 8, 2006“Bus Stuttering”8 Why is packaging limiting performance? Package Parasitics Limit Performance - Excess inductance causes package noise - Noise limits how fast the package can transmit data 1.Supply Bounce (due to self inductance of VDD/GND bondwires) 2.Signal Coupling (due to mutual inductance between nearby signal bondwires)

9 March 8, 2006“Bus Stuttering”9 Why is packaging limiting performance? Aggressive Package Design Helps, but is expensive… - 95% of ASIC design-starts are wire bonded - Goal: Extend the life of current packages QFP – Wire Bond : ~ 4.5nH  $0.22 / pin BGA – Wire Bond : ~ 3.7nH  $0.34 / pin BGA – Flip-Chip : ~ 1.2nH  $0.63 / pin

10 March 8, 2006“Bus Stuttering”10 Our Solution “Encode Off-Chip Data to Avoid Inductive Cross-talk” Avoid the following cases: 1) Excessive switching in the same direction = reduce ground/power bounce 2) Excessive X-talk on a signal when switching = reduce edge degradation 3) Excessive X-talk on signal when static = reduce glitching

11 March 8, 2006“Bus Stuttering”11 Our Solution This results in: 1) A subset of vectors is transmitted that avoids inductive X-talk. 2) The off-chip bus can now be ran at a higher data rate. 3) The subset of vectors running faster can achieve a higher throughput over the original set of vectors running slower (including overhead). Throughput Throughput of less vectors of more vectors at higher data-rate at lower data-rate

12 March 8, 2006“Bus Stuttering”12 Bus Stuttering CODEC Intermediate States are Inserted Between Noise Causing Transitions - Stutter states limit the number of simultaneously switching signals - The source synchronous clock is gated during stutter state Package Un-encoded: B  C Vector Sequence Causes Noise Limit Violation Package Encoded: B  C Vector Sequence is eliminated using Stutter BAC BAC BAC Encoder Core No Encoding w/ Encoding BAC BAC BAC BAC BAC BAC A B stutterCA B CA B C

13 March 8, 2006“Bus Stuttering”13 Simultaneous Switching Noise Supply Bounce Induced Self Voltage Glitching Coupling onto Non-Switching Signals Edge Degradation Coupling onto Switching Signals Data Dependent Delay Bus Stuttering CODEC – Noise Sources

14 March 8, 2006“Bus Stuttering”14 Terminology Define the following: n =width of the bus segment where each bus segment consists of n-2 signals and 1 V DD and 1 V SS. j = the segment consisting of an n-bit bus. j is the segment under consideration. j-1 is the segment to the immediate left. j+1 is the segment to the immediate right. each segment has the same V DD /V SS placement.

15 March 8, 2006“Bus Stuttering”15 Terminology Define the following: =the transition (vector sequence) that the i th signal in the j th segment is undergoing, where = 1 = rising edge = -1 = falling edge = 0 = signal is static This 3-valued algebra enables us to model mutual inductive coupling of any sign

16 March 8, 2006“Bus Stuttering”16 Terminology Define the following coding constraints: Supply Bounce if is a supply pin, the total bounce on this pin is bounded by P bnc. P bnc is a user defined constant. Glitching if is a signal pin and is static ( = 0), the total magnitude of the glitch from switching neighbors should be less than P 0. P 0 is a user defined constant. Edge Degradation if is a signal pin and is switching ( = 1/-1), the total magnitude of the coupling from switching neighbors should be greater than P 1 / P -1. This coupling should not hurt (should aid) the transition. P 1 / P -1 is a user defined constant.

17 March 8, 2006“Bus Stuttering”17 Terminology Also define the following: p = how far away to consider coupling (ex., p = 3, consider K 11, K 12, and K 13 on each side of the victim) k q =Magnitude of coupled voltage on pin i when its q th neighbor p switches:

18 March 8, 2006“Bus Stuttering”18 Methodology For each pin v i j within segment j, we will write a series of constraints that will bound the inductive cross-talk magnitude. The constraints will differ depending on whether v i j is a signal or power pin. The coupling constraints will consider signals in adjacent segments (j+1, j-1) depending on p.

19 March 8, 2006“Bus Stuttering”19 Methodology Glitching : coupling is bounded by P 0 Example: v 2 j =0, and p=3. This means the three adjacent neighbors on either side of v 2 j need to be considered (v 4 j-1, v 0 j, v 1 j, v 3 j, v 4 j, v 0 j+1 ). Note we use modulo n arithmetic (and consider adjacent segments as required). v 2 j = 0 (static) -P 0 < k 3 ·(v 4 j-1 ) + k 2 ·(v 0 j ) + k 1 ·(v 1 j ) + k 1 ·(v 3 j ) + k 2 ·(v 4 j ) + k 3 ·(v 0 j+1 ) < P 0 The constraint equation is tested against each possible transition and the transitions that violate the constraint are eliminated. 0000

20 March 8, 2006“Bus Stuttering”20 Methodology Edge Degradation : coupling is bounded by P 1 and P - 1 Example: v 2 j = 1 or -1, and p = 3. This means the three adjacent neighbors on either side of v 2 j need to be considered (v 4 j-1, v 0 j, v 1 j, v 3 j, v 4 j, v 0 j+1 ). v 2 j = 1 (rising) k 3 ·(v 4 j-1 ) + k 2 ·(v 0 j ) + k 1 ·(v 1 j ) + k 1 ·(v 3 j ) + k 2 ·(v 4 j ) + k 3 ·(v 0 j+1 ) > P 1 v 2 j = -1 (falling) k 3 ·(v 4 j-1 ) + k 2 ·(v 0 j ) + k 1 ·(v 1 j ) + k 1 ·(v 3 j ) + k 2 ·(v 4 j ) + k 3 ·(v 0 j+1 ) < P - 1 Again, the constraint equations are tested against each possible transition and the transitions that violate the constraints are eliminated. 0000 0000

21 March 8, 2006“Bus Stuttering”21 Methodology Supply Bounce : coupling is bounded by P bnc Example: v 0 j =V DD or V SS. The total number of switching signals that use v 0 j to return current must be considered. Due to symmetry of the bus arrangement, signal pins will always return current through two supply pins. i.e., (v 0 j-1 and v 0 j ) or (v 4 j and v 4 j+1 ). This results in the self inductance of the return path being divided by 2. Let z = |L di/dt| for any pin. Then, v 0 j = V DD (z/2)·(# of v i j pins that are 1) < P bnc v 4 j = V SS (z/2)·(# of v i j pins that are -1) < P bnc

22 March 8, 2006“Bus Stuttering”22 Methodology For each bit in the j th segment bus, constraints are written. If the pin is a signal, 3 constraint equations are written; - v 0 j = 0, the bit is static and a glitching constraint is written - v 0 j = 1, the bit is rising and an edge degradation constraint is written. - v 0 j = -1, the bit is falling and an edge degradation constraint is written. If the pin is V DD, 1 constraint equation is written to avoid supply bounce. If the pin is V SS, 1 constraint equation is written to avoid ground bounce. For the segment, 1 constraint equation is written to constrain power.

23 March 8, 2006“Bus Stuttering”23 Methodology This results in the total number of constraint equations written is: (3·n – 4) Each equation must be evaluated for each possible transition to verify if the transition meets the constraints. The total number of transitions that are evaluated depends on n and p: 3 (n+2p – 6) This follows since there are n-2 signal pins in the segment j, and 2p-4 signal pins in neighboring segments. The values of n and p are small in practice, hence this is tractable.

24 March 8, 2006“Bus Stuttering”24 Example # of Constraints = (3n – 4) = 11 1) v 0 j = V DD  (L/2)· (# of v i j pins that are 1) P 1 3) v 1 j = -1  k 1 · (v 2 j ) + k 2 · (v 3 j ) P 1 6) v 2 j = -1  k 1 · (v 1 j ) + k 1 · (v 3 j ) P 1 9) v 3 j = -1  k 2 · (v 1 j ) + k 1 · (v 2 j ) < P -1 10) v 3 j = 0  - P 0 < k 2 · (v 1 j ) + k 1 · (v 2 j ) < P 0 11) v 4 j = V SS  (L/2)· (# of v i j pins that are -1) < P bnc

25 March 8, 2006“Bus Stuttering”25 Example Transitions Eliminated due to Constraint Violations Rule(s) Violated Transition AggressiveNon Aggressive 011 violates 1,4 - 0-1-1 violates 4,11 - 101 violates 1,7 - 110 violates 1,10 - 111 violates 1,2,5,8 violates 11 11-1 violates 1 - 1-11 violates 1 - 1-1-1 violates 11 - -10-1 violates 7,11 - -111 violates 1 - -11-1 violates 11 - -1-10 violates 10,11 - -1-11 violates 11 - -1-1-1 violates 3,6,9,11 violates 1

26 March 8, 2006“Bus Stuttering”26 Directed graph is created from surviving legal transitions Directed Graph is Used to Map Transitions Between any Two Vectors - A transition path (which may include stutters) exists between any two vectors if: There exists at least two outgoing edges for each vector v s  G (including self-edge) There exists at least two incoming edges for each vector v d  G (including self-edge) Bus Stuttering CODEC - Algorithm G

27 March 8, 2006“Bus Stuttering”27 Bus Stuttering CODEC - Construction Multiple Stutter States can be used - Between 0 and 2 (W bus -1) stutters can be inserted between any two vectors - Results show that for segments up to 8 bits, more than 3 stutters is rare Overhead - Overhead increases as segments sizes increase - Still useful since segments greater than 8 bits are rarely used.

28 March 8, 2006“Bus Stuttering”28 Bus Stuttering CODEC – Physical Results Circuit Implementation - 32 pipeline stages used - Pipeline reset after 32 idle states (similar to SRIO, HT, and PCI Express) - Protocol inherently handles pipeline overflow

29 March 8, 2006“Bus Stuttering”29 SPICE Simulations - 3 bit segment (5 pins including VDD and GND) - Fixed di/dt - Maximum noise reduced by limiting simultaneously switching signals SPICE simulations match analytical predictions with great fidelity Bus Stuttering CODEC – Physical Results Ground Bounce GlitchingEdge Degradation

30 March 8, 2006“Bus Stuttering”30 Bus Stuttering CODEC – Physical Results TSMC 0.13um Synthesis Results - RTL design, synthesized and mapped - Segment sizes 2  8 implemented - Logic, delay, and area evaluated

31 March 8, 2006“Bus Stuttering”31 Bus Stuttering CODEC – Physical Results Xilinx FPGA, 0.35um Implementation Results - RTL design implemented - Xilinx, VirtexIIPro, FPGA

32 March 8, 2006“Bus Stuttering”32 Bus Stuttering CODEC – Physical Results Xilinx FPGA, 0.35um Implementation Results - RTL design, implemented - Logic operation verified - Noise Reduced from 16% to 4% (Segments with 4 signal pins)

33 March 8, 2006“Bus Stuttering”33 Conclusion Packaging Performance is the Largest System Bottleneck Stutter Encoding Avoids Worst-Case Noise Patterns Performance Improved Even After Considering Encoding Overhead

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