1. Imperium Accelero 9K Group Members Ian Ferguson Nathan Liesch Luis Ramirez Mark Willson

2. Overview Image Processing / DSP on a FPGA IA9K operates on 96x64 8-bit Grayscale Uncompressed Bitmaps IA9K attempts to streamline sequential filtering algorithms by taking advantage of 2 memory controllers 3x3 Convolution and Linear Filters are the basis of the IA9K Image Processing

3. Features 8-bit Video Display RS232 Upload / Download LCD User Interface 2 LPM RAM Memory Controllers 3x3 Convolution Module Linear Filter Module

4. RS-232 Detects data sent serially from PC and converts to 24-bit signal sent to RAM Data can be received at 9600 or 19200 baud depending on clock dividers Will only accept data inside valid RS232 packets by sensing start and stop bits. No parity. 10 second timeout

5. From SDRAM to LPM_RAM SDRAM: Much more capacity (128MB) Pre-built SDRAM controller Requires a complex memory controller LPM_RAM: Easy to implement Can be simulated Simple interface Limited capacity to 106,496 bits

6. Memory Controller Controls access to ram Developed 3 access modes:  Write  Read (no handshake signals)  Read (with handshake signals) Random access of memory is not required Design implements two instances of the memory controller

7. Display 96 x 64 image expanded to 576 x 384 resolution 8bit grayscale output 33MHz pixel clock

8. User Interface User Commands are sent via 2 push buttons (Enter and Select) Menu and Status Messages are displayed using a 2x16 char LCD IA9K Modules are disabled at startup and enabled / disabled as needed by the User Interface Modules are responsible for their own Interactions with other modules

9. UI Control Flow

10. UI Data Flow

11. Filters 3x3 Shift Register 3x3 Convolution Calculation Pixel-by-Pixel Calculations 2 stages of buffering are used in the reading and writing of image data in order to achieve one result every clock cycle

12. Pixel-by-Pixel Manipulations Sequential access of pixel data Calculate new pixel value independently of surrounding pixels NegativeThreshold

13. 3x3 Shift Register Shift Register is large enough to store 2 complete rows of image data plus 3 additional pixels

14. 2D Convolver the heart of the system is the fully programmable 3x3 convolver 8bit image data and 9bit signed coefficient kernel weights allows for a wide range of filters to be applied blur, sharpen, edge enhance, find edges, and emboss required significant pipelining to match rest of system uses adder trees, pipelined multipliers and dividers to yield one result per clock cycle

15. Java Convolution Demo

16. Summary of Filters Light BlurHeavy BlurEdge Enhance EmbossSharpenFind Edge Images generated by GIMP Original 111 111 111 121 242 121 9 00 000 001 -2 -216-2 -2 8

17. IA9K Stats 7544 / 8320 (91%) Logical Elements Used 98k / 106k (92%) Memory Elements Used 3x3 Convolution Filter takes approx 190us Linear Filter takes approx 185us Max Simulated Frequency ~50MHz RS232 currently runs 9600 bps

18. Questions? From anyone other than Jason?

19. Accomplishments 3 forests killed Quad 720 O synchronized rolly chair spin 90m 5-storey paper airplane flight 4:42:54 max simulation length 29 Sun workstation crashes 1500 man-hours of work 24L of beer consumed