1. Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, Patrick Palmer University of British Columbia (UBC) Vancouver, BC, Canada A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter

2. 2 Motivation Power-limited CPU performance –Trend: > 4 CPU cores on one chip Solution? –Dynamic Voltage and Frequency Scaling (DVFS) - Each core scaled differently based on load –Need multiple supply voltages on-chip

3. 3 Motivation How to supply multiple voltages? Our approach … –Global voltage distribution (high V dd ) –Local voltage regulation (on-chip, low V dd ) Support for … –Coarse-grain voltage islands (e.g., CPU cores) –Fine-grain voltage islands (e.g., ALU, FPU, …)  On-chip “local” voltage regulation

4. 4 Problem Definition On-chip “local” voltage regulation Constraints –On-chip components, “standard” CMOS –Scaled down voltage  buck converters Shrink L, C to fit on-chip –Efficiency trade-off Local regulator consumes power Local regulator saves power by DVFS  consumption < savings 

5. 5 Summary Results On-chip DC-DC buck (step-down) converter –Standard 90nm CMOS –1V input, 0.5~0.7V output, 100mA –Up to 158% effective efficiency Over 100% !!!??? –By recycling charge thrown away in clock tree High-speed operation –3GHz CPU clock  3GHz buck converter Monolithic L and C (converter area 0.27mm 2 ) –Unique ZVS delay circuit improves efficiency

6. 6 Switch Mode Power Supply CMOS inverter as power switches in buck converter

7. 7 Clock and SMPS Merging CPU clock: 3GHz clock and large C clk SMPS: large M p, M n drive chain

8. 8 Clock and SMPS Merging Combine the driver circuits

9. 9 Key Contribution: CHARGE RECYCLING Benefits –Shared driver chain –C clk added to SMPS Note: NMOS drains C clk, wastes charge! Delaying NMOS  ZVS recycles clock charge!

10. 10 ZVS Detailed Operation ZVS delay circuit  –Delay only rising edge of V n –Implemented inside the clock chain

11. 11 ZVS Detailed Operation (Mode 1) Mode 1 (0 < t < D  T sw ) –M p is ON –Current builds up in the inductor –C clk charges up D = Duty cycle T sw = Switching period

12. 12 ZVS Detailed Operation (Mode 2) Mode 2 (D  T sw < t < D  T sw +T zvs ) –Both power transistors are OFF –Inductor current discharges C clk –C clk charge is recycled to output load D = Duty cycle T sw = Period T zvs = ZVS delay

13. 13 ZVS Detailed Operation (Mode 3) Mode 3 (D  T sw +T zvs < t < T sw ) –M n turns ON when V clk  0 ZVS for M n –Inductor current decreases linearly D = Duty cycle T sw = Period T zvs = ZVS delay

14. 14 Detailed Operation ZVS delay circuit for M n –Delay rising edge of V n

15. 15 Detailed Operation Adaptive ZVS delay circuit for M n –Falling edges of V p and V n are synchronized

16. 16 Implementation Chip 1mm 2, converter 0.27mm 2

17. 17 Implementation Charge recycling of the clock tree capacitor Reference clock circuit Circuit 2, P in2 Combined SMPS + clock circuit Circuit 1, P in1, P out1

18. 18 Power Conversion Efficiency P out1 = output power (delivered to load) P in1 – P in2 = incremental power to operate SMPS only P in1 = power of combined SMPS + clock circuit P in2 = power of reference clock circuit Efficiency (raw) Efficiency (effective)

19. 19 Comparative Results This Work[JSSC05][ISSCC06] TypeBuck4-Phase Buck2-Phase Buck Technology90nm CMOS 0.18µm SiGe RF BiCMOS Switching freq, F sw (MHz)300023345 Input voltage, V in (V)1.01.2 to 1.42.8 Output voltage, V out (V)0.5 to 0.70.9 to 1.11.5 to 2 Output ripple (%-pp)< 5 % (V out =0.7V) Output current, I out (mA)40 to 100300 to 400200 Effective efficiency  eff (%) 158 % (V out =0.7V) 98 % (V out =0.6V) 80 % (V out =0.5V) 84 %65 % Filter inductor, L f (nH)0.326.8 (per phase)11 (per phase) Filter capacitor, C f (pF)35025006000 Off/on chip L f, C f On-chipOff-chip LOn-chip Converter area (mm 2 )0.270.14 (excl. L & C)27

20. 20 Contributions Key concepts –High switching frequency  saves area –Combined drivers  saves area and switching loss –Recycled charge  converter load discharges C clk –Unique ZVS delay circuit  lower power loss Limitations –Regulation needs variable duty cycle clock May introduce additional clock jitter Mostly suitable for edge-triggered blocks (no latches)

21. 21 References [JSSC05] P. Hazucha, G. Schrom, H. Jaehong, B. A. Bloechel, P. Hack, G. E. Dermer, S. Narendra, D. Gardner, T. Karnik, V. De, and S. Borkar, “A 233MHz 80%-87% Efficient Four- Phase DC-DC Converter Utilizing Air-Core Inductors on Package,” IEEE J. Solid-State Circuits, vol. 40, pp. 838- 845, Apr., 2005. [ISSCC06] S. Abedinpour, B. Bakkaloglu, and S. Kiaei, “A Multi-Stage Interleaved Synchronous Buck Converter with Integrated Output Filter in a 0.18µm SiGe Process,” ISSCC Dig. Tech. Papers, pp. 356-357, Feb., 2006.