1. LECC 2002 - COLMAR - Alessandro Gabrielli1 Realization and Test of a 0.25  m Rad-Hard Chip for ALICE ITS Data Acquisition Chain Davide Falchieri - Alessandro Gabrielli - Enzo Gandolfi Physics Department - Bologna University - Viale Berti Pichat 6/2 40127 Bologna - Italy - Tel. +39-051-2095077 FAX: +39-051-2095297

2. LECC 2002 - COLMAR - Alessandro Gabrielli2 Talk Overview Work presentation and ALICE internal note ALICE ITS and DAQ chain Chip CARLOS 2.0 presentation (layout views and main features) Digital Design Flow Instruments of the laboratory - SIU DAQ chain and Tests performed at Bologna and at CERN Future work plan

3. LECC 2002 - COLMAR - Alessandro Gabrielli3 DAQ Chain Test @ CERN CARLOS_rx SIU Ext SIU CARLOS 2.0

4. LECC 2002 - COLMAR - Alessandro Gabrielli4 CERN – ALICE Internal Note ALICE-INT-2002-24 1.0 Collaboration:  EP/MIC group at CERN (digital library and design support)  ALICE/DAQ group at CERN (SIMU and SIU boards)

5. LECC 2002 - COLMAR - Alessandro Gabrielli5 ALICE Inner Tracking System  The Inner Tracking System (ITS) is made by 6 cylindrical layers of silicon wafers like  The Silicon Drift Detector is made of layers 3 and 4 of ITS Layer 3 has 14 ladders with 6 detectors each Layer 4 has 22 ladders with 8 detectors each  Each detector serves 2 channels that provide 8-bit data @ 40 MHz  Thus 260 CARLOS chips are required

6. LECC 2002 - COLMAR - Alessandro Gabrielli6 ALICE DAQ System

7. LECC 2002 - COLMAR - Alessandro Gabrielli7 CARLOS 2.0 main features - Huffman-like coding: no compression algorithm at the moment - Data Packing - Dual Port FIFOs - JTAG and interfaces - Internal 200-word BIST

8. LECC 2002 - COLMAR - Alessandro Gabrielli8 CARLOS 2.0 layout views Core Final Layout 4x4 mm 2 100 Pads VDD GND wires

9. LECC 2002 - COLMAR - Alessandro Gabrielli9 CARLOS 2.0 layout views Clock buffered tree Clock Components Leaf Cells Pad_Ck out 86 1644 Timing Pad_Ck Max. transition time at leaf pins:0.258 ns Min. insertion delay to leaf pins:0.698 ns Max. insertion delay to leaf pins:0.770 ns Max. skew between leaf pins:0.072 ns

10. LECC 2002 - COLMAR - Alessandro Gabrielli10 CARLOS 2.0 layout views Rad-Hard Cells Power Wires designed by hand

11. LECC 2002 - COLMAR - Alessandro Gabrielli11 Digital Design Flow VHDL Front-End (Synopsys) Functional Verification VSS (Synopsys) Synthesis (Synopsys) - VERILOG Netlist import (Cadence SE) – Manual Modifications Pre-Layout Verification (Verilog-XL & Verilog test patterns Cadence) Back-End Design – Floorplanning and Pad-Placements PEARL Timing Analisys (Cadence) Post-Layout validation (Verilog-XL & Verilog test patterns Cadence) Full-Custom VDD and GND connections (Cadence) Diva DRC & LVS Stream-Out (GDS2) Silicon Foundry CARLOS 2.0 Back-End Design – Cell-Placement, Clock-Tree-Generation, Routing

12. LECC 2002 - COLMAR - Alessandro Gabrielli12 Laboratory set-up Tektronix Pattern generator & Logic Analyzer Oscilloscope Voltage suppliers TPG probes: 68 channels TLA probes: 64 channels

13. LECC 2002 - COLMAR - Alessandro Gabrielli13 SIU photo by CERN/DAQ group

14. LECC 2002 - COLMAR - Alessandro Gabrielli14 GOL DES 16 200 m Rx HDMP-1034 rx-ck rxdat a 8 ½ SDD A P A P 8 txdata 16 32 JTAG TTC_rx The whole Readout Chain txdata 16 32 JTAG Test performed @ CERN on June 14th 2002 RAD-HARD Electronics Q-PLL CARLOS 2.0 CARLOS-rx SIU Pattern Generator Logic Analyzer

15. LECC 2002 - COLMAR - Alessandro Gabrielli15 CARLOS2.0 SIMU CARLOS_rx Chain test CARLOS 2.0 to SIMU @ Bologna The SIMU (SIU-DDL emulator) opens a transaction data transmission from CARLOS 2.0 data to SIMU via CARLOS_rx SIU Ext

16. LECC 2002 - COLMAR - Alessandro Gabrielli16 Chain test with the DDL @ CERN test-bench (4k) txdata 16 32 JTAG The SIMU has been disconnected and replaced by the DDL chain The opening of a transaction has been issued by the PC linked to the pRORC by means of a 200m optical fiber Data have been acquired both by the logic analyzer and by the DDL chain using the software DATE v4: 83.000 data packets have been successfully transmitted by the pattern generator and stored using the DDL. 40 MHz 20 MHz 40 MHz pRORC CARLOS 2.0 CARLOS-rx DIU DDL SIU Pattern Generator Logic Analyzer

17. LECC 2002 - COLMAR - Alessandro Gabrielli17 Chain test with the DDL @ CERN CARLOS_rx SIU Ext CARLOS 2.0 SIU

18. LECC 2002 - COLMAR - Alessandro Gabrielli18 CARLOS 2.0 – Test @ Bologna

19. LECC 2002 - COLMAR - Alessandro Gabrielli19 CARLOS 3.0 with 2D compressor prototype design, developement and MPW submission: estimated area: (4x4  4x6) mm 2 Test board for CARLOS3.0 with Fine-Pitch-BGA package for: - prototypes testing purposes on a dedicated test board with a ZIF socket - yield evaluations on (production) chips thanks to the packaging low cost - optical rad-hard link bewteen CARLOS and Carlos_rx boards Design of the final version of DAQ chain Bologna work plan 2002-2003