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Torsten Alt - KIP Heidelberg IRTG 28/02/2007 1 ALICE High Level Trigger The ALICE High-Level-Trigger.

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Presentation on theme: "Torsten Alt - KIP Heidelberg IRTG 28/02/2007 1 ALICE High Level Trigger The ALICE High-Level-Trigger."— Presentation transcript:

1 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 1 ALICE High Level Trigger The ALICE High-Level-Trigger

2 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 2 Overview The ALICE High-Level-Trigger: dataflow in the ALICE experiment trigger systems : L0, L1, L2 TPC – largest datasource High-Level-Trigger: Tasks & Implementation The HLT ReadOut-Receiver-Card (H-RORC): Tasks & Requirements Implementation

3 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 3 The ALICE detector ITS : Inner Tracking SystemTPC : Time Projection Chamber TRD : Transition Radiation Detector

4 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 4 Trigger L0 - 1.2µs : event occured L1 – 6.5µs : start sampling in the Front-End-Electronics L2 – 88µs : readout data from the Front-End-Electronics data buffer L0, L1, L2 look for „valid“ events and trigger the readout!

5 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 5 High-Level-Trigger : HLT Needs for a High-Level-Trigger: the sub-detectors produce more data than a permanent tape storage system can handle Online analysis allows to trigger for rare events i.e. jets Events can be „tagged“ to prepare them for later offline analysis

6 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 6 HLT - Dataflow TPC DiMuon TRD ITS HLT Permanent Storage

7 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 7 HLT - Dataflow TPC DiMuon TRD ITS HLT Permanent Storage IN: 16 GB/s OUT: < 1,2 GB/s

8 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 8 Picture of the ALICE TPC Sector P.Glaessel – will be replaced by ITS later

9 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 9 Event in the STAR TPC

10 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 10 TPC Read-Out Electronics OROC IROCrow pad 2 x 18 sectors ( Side A & C) 6 readout partitions (patch) per sector : 216 patches ~ 26 rows per patch ~ 90 pads per row = 557,568 pads

11 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 11 HLT Infrastructure for one TPC sector TPC sector TR TDS Front-End Processors second sector HLT - cluster FEP CFRPH-RORC BDW RPH-RORC BDW FEP H-RORC BDW H-RORC BDW FEP H-RORC BDW CFRPH-RORC BDW CF RP CFRP CFRP DAQ HLT Online Display reconstrcution data flow display data flow

12 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 12 Tracking in the HLT Raw Data(Ordering, Zero Suppression) Cluster Finding (in readout partition) Tracking (Conformal-Mapping / Track Follower) - Data amount + Computing amount Can be done in the FPGA

13 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 13 Clusterfinding 1

14 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 14 Clusterfinding 2

15 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 15 HLT in the pit – Counting Room 2 &3 CR 2 & 3 : HLT ALICE Beampipe

16 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 16 The HLT Cluster First Stage : Installation will take place from 28.2 to 7.3. 80 server with 2 x DualCore Opteron Each server will be equipped with 2 RORCs Each server will be equipped with a remote control system : CHARM 216 incoming DDLs for the TPC 10 outgoing DDLs to the DAQ HLT Prototype at KIP

17 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 17 The H-RORC

18 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 18 H-RORC Block diagramm XILINX VIRTEX4 LX40 DDR-SD TAGNET USER- FLASH CFG- FLASH PLATFORM PROM XC95144 CPLD CMC-Connector Power 1V2 Power 2V5 Power 1V8 TAGNET RS-232 ETH-PHY PCI-66/64 PCI-Power 3V3 MemoryConfiguration Serial links LVDS links POWER CMC-J11/J22 OSC

19 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 19 H-RORC Overview H-RORC : HLT Read-Out Receiver Card Tasks: –Receiving of the raw detector data –Injecting the data into the main memory of the hosts of the HLT framework –Online processing of the data in hardware –Sending processed data out of the HLT –Serve as a developing platform for new designs Requirements : - Flexible and modulare architecure - Possibility to upgrade to larger FPGAs - Safe update of the firmware

20 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 20 Clusterfinding in the FPGA 1 Each datapoint is represented by 4-dimensional vector (row, pad, time, charge) Processing can by done for each row independently: Clusterfinding is a parallel process Clusterfinder operates on (pad, time, charge) Main operations: add, multiply, compare, store Main operations can be done in parallel

21 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 21 Clusterfinding in the FPGA 2 1.stage: CF-DECODER CF calculate the weighted time, the sequential charge and the total charge. 2.stage: CF-MERGER The values are compared and merged if they correspond 3.stage: DATA-MERGER The clusters are written to a memory Pad Time Add & MultiplyCompare & AddStore DecoderRAWMergerData-Merger Clusterfinder

22 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 22 Secure Configuration XILINX VIRTEX4 LX40 DDR-SD TAGNET USER- FLASH CFG- FLASH PLATFORM PROM XC95144 CPLD CMC-Connector Power 1V2 Power 2V5 Power 1V8 TAGNET RS-232 ETH-PHY PCI-66/64 PCI-Power 3V3 MemoryConfiguration Serial links LVDS links POWER CMC-J11/J22 OSC

23 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 23 SecureConf USER 1 USER 2 FLASH CPLD PCI Virtex4 FPGA Write A user configuration can be written to the FLASH via PCI. Depending on the size of the FLASH several user configurations can be stored. Secure Configuration 2

24 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 24 SecureConf USER 1 USER 2 FLASH CPLD PCI Virtex4 FPGA The CPLD checks the FLASH for a valid user configuration and the FPGA is then configured with this configuration Configuration data CTRL CTRL/STATUS Secure Configuration 3

25 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 25 SecureConf USER 1 USER 2 FLASH CPLD PCI Virtex4 FPGA After configuration a watchdog is enabled inside the CPLD. It needs to be disabled by a defined sequence send via PCI. If anything goes wrong and the watchdog isn`t disabled, it will time out and the FPGA will be reconfigured with the SecureConf. WATCHDOG Secure Configuration 4

26 Torsten Alt - KIP Heidelberg IRTG 28/02/2007 26 SecureConf USER 1 USER 2 FLASH CPLD PCI Virtex4 FPGA The watchdog has timed out and the FPGA is reconfigured with the SecureConf. The SecureConf contains a design which will always give access to the FLASH via PCI. Configuration data CTRL CTRL/STATUS WATCHDOG Secure Configuration 5

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