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6/3/20151 Developing a multi-thread product – Introduction (ENCM491 – real time operating systems in 1 hr) M. Smith Electrical Engineering, University.

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Presentation on theme: "6/3/20151 Developing a multi-thread product – Introduction (ENCM491 – real time operating systems in 1 hr) M. Smith Electrical Engineering, University."— Presentation transcript:

1 6/3/20151 Developing a multi-thread product – Introduction (ENCM491 – real time operating systems in 1 hr) M. Smith Electrical Engineering, University of Calgary Smithmr @ ucalgary.ca

2 6/3/20152 / 45 References 1) Understanding GPS Principles and Applications, 1996, Elliott D. Kaplan 2) Digital Signal Processing – A Practical Approach, 1993, Emmanuel C. Ifeachor, Barrie W. Jervis 3) ADSP-TS101 TigerSHARC and Blackfin Processor Programming References, Analog Devices 4) Articles submitted to Circuit Cellar magazine by M. Smith, March 2004

3 6/3/20153 / 45 Introduction GPS traditionally done with ASIC/Processor combination Looking at FPGA/DSP combination for low end GPS receivers Technological interest in software radio  Cheaper, quicker development cycle.  Customizations for special applications From a talk by Darrell Anklovitch for ENEL619.23

4 6/3/20154 / 45 What is GPS? Global Positioning System 24 satellite (SV) constellation Orbits are set-up to give global coverage 24 hours a day Need at least 4 satellites in view to calculate a position Orbiting 20,000 km from the surface of the Earth in 12 hour cycles (1)

5 6/3/20155 / 45 GPS Positioning Concepts (1) For now make 2 assumptions:  We know the distance to each satellite  We know where each satellite is Require 3 satellites for a 3-D position in this “ideal” scenario Requires 4 satellites to account for local receiver clock drift.

6 6/3/20156 / 45 GPS Signal Structure Each satellite transmits 2 carrier frequencies referred to as L1 (1575 MHz) and L2 (1227 MHz) Each carrier frequency is BPSK modulated with a unique PRN (pseudo random number) code The PRN code on L1 is called CA code (coarse acquisition), The PRN code on L2 is called P code (precise) CA code takes 1 ms for full PRN transmission at 1MHz chip (bit) rate. P code takes 1.5 s for full PRN transmission at ~10MHz chip rate Also modulated on each carrier is 50 Hz data that includes the current position of the satellite

7 6/3/20157 / 45 Determining Time Use the PRN code to determine time Use time to determine distance to the satellite distance = speed of light * time (1)

8 6/3/20158 / 45 Algorithms to Find PRN Phase Time-domain Cross correlation: 1/N ∑ x 1 (n) * x 2 (n)  Coding equivalent to FIR filter, but need to filter N sets of data, each shifted by one data point – looks like a final exam question to me. Correlation of perfectly matching signals gives a maximum value Correlation of 2 random data sequences tends to 0  PRN code from different satellites are designed to correlate to 0. Frequency domain correlation: 1/N F -1 [X 1 (k)X 2 (k)] where F -1 is the inverse Discrete Fourier Transform and the X’s are the Discrete Fourier Transforms of two sequences D

9 6/3/20159 / 45 Frequency Domain 1/N F -1 [X 1 (k)X 2 (k)]  1024 point FFT(2 * NLOG 2 N)  1024 MULTS(N)  1024 point INV FFT(NLOG 2 N) Time Domain 1/N ∑ x 1 (n) * x 2 (n) n = 0  1024 MACs(N)  1024 Phases(N) Timing 30,000 Complex operations 1,048,576 operations N-1 (N 2 )

10 6/3/201510 / 45 TigerSHARC -- TS101 and TS201 Low-cost version $45 / chip Evaluation boards $950 each educational price TS101 TS201 Can do “COMPLEX” arithmetic

11 6/3/201511 / 45 Implementing a multi-thread system working on batch data – “audio example” Collect N pts @ 44 kHz  array1 Collect N pts @ 44 kHz  array2 Collect N pts @ 44 kHz  array3 Collect N pts @ 44 kHz  array1 Collect N pts @ 44 kHz  array2 Process array1 Process array2 Process array3 Process array4 Transmit N pts @ 44 kHz  array1 Transmit N pts @ 44 kHz  array2 Transmit N pts @ 44 kHz  array3

12 6/3/201512 / 45 Implementing a multi-thread system -- “audio example” Collect N pts @ 44 kHz  array1 Collect N pts @ 44 kHz  array2 Collect N pts @ 44 kHz  array3 Collect N pts @ 44 kHz  array1 Collect N pts @ 44 kHz  array2 Move array1  array4 SimulateComplex Move array2  array5 SimulateComplex Move array3  array6 SimulateComplex Move array1  array4 SimulateComplex Transmit N pts @ 44 kHz  array4 Transmit N pts @ 44 kHz  array5 Transmit N pts @ 44 kHz  array6

13 6/3/201513 / 45 Essentially Take an audio Talk-through program for loop { Read_a_sample; Perform operation; Write_a_sample; } Turn into 5-threads running under interrupts  Idle thread  Initialization thread – sets up system, when ready – launches the other threads – then activates the first thread  ReadValueThread,  ProcessValueThread – with simulated Complex Algorithm  WriteValueThread

14 6/3/201514 / 45 Initialization Thread

15 6/3/201515 / 45 Main Thread – example

16 6/3/201516 / 45 Need to investigate and understand system behaviour and limitations Concept of task priority

17 6/3/201517 / 45 Using real-time audio-threads -- Write

18 6/3/201518 / 45 VDK – Status History

19 6/3/201519 / 45 Adding the Initialization thread

20 6/3/201520 / 45 Making the InitializationThread a “Boot Thread”

21 6/3/201521 / 45 Add the thread programming control

22 6/3/201522 / 45 Avoid the free-running code

23 6/3/201523 / 45 Then add semaphores to control flow

24 6/3/201524 / 45 Essential, if not exact, concept of multi- threading code Do all the initial preparation of the board  Set up stack  Set up “C/C++” environment  Set up processor timer Default on Blackfin ADSP-BF533 board – every 0.05 ms (called a TIC) an interrupt occurrs Start with an IDLE Thread When first TIC occurs – the interrupt handler will cause the Scheduler ISR to run

25 6/3/201525 / 45 Scheduler ISR Save all the registers (etc) of the IDLE thread to the IDLE thread context buffer Recover all the registers for the scheduler ISR context buffer (saved somewhere during the initialization procedure) There had better be a boot thread – otherwise system hangs  VDK tool will not let you build a system without at least one boot thread Decide which boot thread has the highest priority? Save all the registers from the Scheduler ISR back into the context buffer Recover all the registers for the boot thread from its context buffer Return from ISR  We have now performed a “context switch” between the IDLE thread and the BOOT thread.

26 6/3/201526 / 45 Boot thread The boot thread now executes until the first TIC occurs (next ISR call) We now switch back into Scheduler  Save all the registers (etc) of the FIRST BOOT THREAD thread to the thread context buffer  Recover all the registers for the scheduler ISR context buffer Other threads need launching?  If there are other Boot threads then launch them depending on their priority and the ROUND ROBIN scheduling behaviour set by the programmer for tasks of equal priority  If a boot thread has requested that other threads need launching then launch those. Unclear when the VDK::CreateThread operation occurs

27 6/3/201527 / 45 The launching of threads Looks like threads get launched “during a TIC” – meaning that another context switch occurs for each VDK::CreateThread ( ) Does that apply to VDK::PostSemaphores( ) too?

28 6/3/201528 / 45 Back in scheduler Other threads need launching?  If there are other Boot threads then launch them depending on their priority and the ROUND ROBIN scheduling behaviour set by the programmer for tasks of equal priority  If a boot thread has requested that other threads need launching then launch those. Have threads posted semaphores?  Store them in a “posted semaphore table.  Threads can also post “messages” but I have not worked that out yet Are threads pending semaphores?  Depending on which task is running now, and its relative priority to tasks that are pending semaphores then either perform context switching or not  How do you handle conflicts? I think that is my problem with my final version of Lab. 5 part 3

29 6/3/201529 / 45 Original audio-talk through program ISR routine Channel to Channel Copy Multi-tasking version of ISR routine

30 6/3/201530 / 45 Step 1 – Add Talk-through program

31 6/3/201531 / 45 Step 2 – Investigate Thread Behaviour

32 6/3/201532 / 45 Step 3 – Fix Thread Behaviour

33 6/3/201533 / 45 Step 4 – Start migrating code to the various threads -- Fix ISR behaviour ORIGINAL NEW VERSION

34 6/3/201534 / 45 Fix Thread Behaviour Initialization thread  Creates other threads and then waits for ever ReadThread  Moves my_In Value  Process Value ProcessThread  Moves Process Value  ProcessDone Value  Calls a “non-optimizable to nothing” routine SimulateMoreComplexProcess(cycles_to_waste) WriteThread  Moves ProcessDone Value  my_Out Value

35 6/3/201535 / 45 Final ReadThread

36 6/3/201536 / 45 Final ProcessThread

37 6/3/201537 / 45 Final WriteThread

38 6/3/201538 / 45 Thread Behaviour depends on Task priorities ALL TASKS HAVE EQUAL PRIORITY WRITE TASK HAS HIGHER PRIORITY THAN PROCESS TASK 1) Read Task – sends semaphore to Process Task 2) Process Task – sends semaphore to Write Task and “starts to waste cycles” 3) Scheduler determines that Write Task can start, send semaphore to Read Task, and finish – and then 4) Scheduler lets Process Task finish (? Why not let Read Task restart?)

39 6/3/201539 / 45 Thread Behaviour Useless as system is “free running” and the signals input and output have no relationship to samples generated by ISR  Some samples repeated many times, others are not  Number of repeats depends on the time that ProcessThread takes to execute

40 6/3/201540 / 45 Need to add an ISR semaphore

41 6/3/201541 / 45 Read Thread – starts on ISR semaphore Blackfin Assembly code looks like 68K With LINK, UNLINK, RTS instructions MACRO STANDARD APPROACH VDK::PostSemaphore( ) DOES NOT WORK

42 6/3/201542 / 45 Many issues still need handling How much time is available before losing sound quality? What are the best priorities for the tasks, and does that priority depend on how much time is spent in ProcessTask? What is the best setting for the task scheduler TIC time (based on processor internal timer)?  Too fast – too much time saving / recovering registers during task switching  Too slow – problems with interrupts being missed or values being over-writtem

43 6/3/201543 / 45 Scheduling based on TIC time DEFAULT TIC = 0.05 ms TIC = 0.005 ms Don’t forget – TICs are shortened

44 6/3/201544 / 45 Which is the Slower / Faster TIC time? Question – how does the thread status history reflect sound quality?


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