1. 1 RAMP White RAMP Retreat, BWRC, Berkeley, CA 20 January 2006 RAMP collaborators: Arvind (MIT), Krste Asanovíc (MIT), Derek Chiou (Texas), James Hoe (CMU), Christos Kozyrakis (Stanford), Shih-Lien Lu (Intel), Mark Oskin (Washington), David Patterson (Berkeley), Jan Rabaey (Berkeley), and John Wawrzynek (Berkeley)

2. 2 RAMP White Goals Large-scale multiprocessor that can boot standard operating systems and run commercial applications Cycle-accurate emulation of target system Cycle-level reproducibility and debugging Unprecedented observability

3. 3 RAMP White Structure DRAM DRAM Cntl. Mem. Sched. Coherence Engine Router L2$ + Coherence CPU + L1$ + Coherenc e To Other Nodes ISA Independent RAMP White uses scalable directory-based coherence protocol Multiple different ISAs will eventually be supported L2$ optional Target router topology independent of host link topology Host DRAM used to support host emulation (e.g., L2 cache image) and tracing, as well as target memory Non-target accesses

4. 4 RAMP White Components RDL & Diagnostic/Debug Architecture (UCB & MIT) Processor+L1$ (Industrial partners)  Need port to RDL (SUN for Niagara) Router (Mark Oskin, UW) 1. single packet router (64 bits to where) 2. Burst transfers 3. reliability Shared L2$ (Krste Asanovic, MIT) Coherence Protocol (James Hoe, CMU) Memory Access Scheduler (Krste Asanovic, MIT) Memory/DRAM controller (UCB)  Starts with BLUE (multiport access/physical) BWRC System Integration (Derek Chiou, UT Austin) All of the above need graduate student contribution.

5. 5 White Implementation Stages White 1.0, 2Q06  64 CPUs, use Xilinx hard PowerPC core  No L2$  Simplest coherence protocol (maybe MSI, or even just MI)  Simple store+forward router White 2.0, 3Q06  128 CPUs, 32-bit soft core  Include L2$  Improved coherence protocol White 3.0, 4Q06  64 CPUs, 64-bit soft core  Cut-through router White 4.0, 1Q07  Multiple ISAs supported  Advanced coherence protocol

6. 6 White Validation Formal verification of implementation  baseline protocol already verified Comparison against C reference model  Convert Verilog into C model (Verilator and/or VTOC)  Compare results while running workloads “Headless” dynamic verification at full speed  CPUs replaced with memory traffic generators and checkers Regression suites at full speed  Run software workloads, compare outputs with reference

7. 7 Contributions for RAMP White NSF/CRI proposal pending for staff  2 full-time staff (one HW/gateware, one OS/software)  Integration, Testing, Documentation, Distribution, etc. UCB/Xilinx ports Microblaze to RDL  Serves in RAMP blue and as an example of processor in RDL  (companies to do the others)