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Dynamic Scan Clock Control In BIST Circuits Priyadharshini Shanmugasundaram Vishwani D. Agrawal

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Presentation on theme: "Dynamic Scan Clock Control In BIST Circuits Priyadharshini Shanmugasundaram Vishwani D. Agrawal"— Presentation transcript:

1 Dynamic Scan Clock Control In BIST Circuits Priyadharshini Shanmugasundaram priyas@nvidia.com Vishwani D. Agrawal vagrawal@eng.auburn.edu

2 Testing of VLSI Circuits and Power High circuit activity during test leads to functional slowdown and high test power dissipation: –Peak power - Large IR drop in power distribution lines Voltage droop and ground bounce (power supply noise) Reduced voltage slows the gates down (delay fault) –Average power - Excessive heating Timing failures Permanent damage to circuit –Good chip may be labeled as bad → yield loss Existing solution: Use worst-case test clock rate to keep average and peak power within specification. –Results in long test time. 3/14/2011ICIT-SSST'112

3 Problem Statement Reduce test time without exceeding the power specification: Proposed solution: Adaptive test clock Use worst-case clock rate when circuit activity is not known Monitor circuit activity and speed up the clock when activity reduces 3/14/2011ICIT-SSST'113

4 Built-In Self-Test (BIST) 3/14/2011ICIT-SSST'11 4 101010101010 Combinational Logic Primary outputs Primary inputs RA: Response analyzer RBG: Random bit generator SSR: Scan shift register (flip-flops with dual inputs) SSR, RBG and RA have common clock and reset Test multiplexers

5 RBG Generates 010101 3/14/2011ICIT-SSST'115 101010101010 Primary outputs Primary inputs RA: Response analyzer RBG: Random bit generator SSR: Scan shift register (flip-flops with dual inputs) SSR, RBG and RA have common clock and reset Test multiplexers

6 RBG Generates 111000 3/14/2011ICIT-SSST'116 000111000111 Primary outputs Primary inputs RA: Response analyzer RBG: Random bit generator SSR: Scan shift register (flip-flops with dual inputs) SSR, RBG and RA have common clock and reset Test multiplexers

7 Main Idea 3/14/2011ICIT-SSST'11 7 Observation: Different sequences of test vector bits consume different amounts of power. Conventional test clock frequency is chosen based on maximum test power consumption. All test vector bits are applied at the same frequency. Test vector bit sequences consuming lower power can be applied at higher clock frequencies without exceeding power budget of the chip.

8 Speeding Up Scan Clock 3/14/2011ICIT-SSST'11 8 Clock periods Cycle power Power budget Clock periods Cycle power Power budget

9 Monitoring Test Activity 3/14/2011ICIT-SSST'119 101010101010 Combinational Logic Primary outputs Primary inputs RA: Response analyzer RBG: Random bit generator Non-transition monitor SSR, RBG and RA have common clock and reset Test multiplexers

10 A Dynamic Scan Architecture 3/14/2011ICIT-SSST'1110

11 Clock Rate vs. SSR Activity 3/14/2011ICIT-SSST'1111 fmax fmax/2 fmax/3 fmax/4 0 N/4 2N/4 3N/4 N Number of non-transitions counted Clock rate N N/2 N/4 0 SSR transitions per clock N = number of flip-flops in scan shift register (SSR) M = number of adjustable clock rates = 4, in this illustration

12 Dynamic Control of Scan Clock 3/14/2011ICIT-SSST'1112 Monitor number of transitions in scan chain Speed-up scan clock when activity in scan chain is low or slow- down scan clock when activity in scan chain is high Number of flip-flops in scan shift register (SSR), N = 8 Number of adjustable clock rates, M = 4 Maximum clock rate, fmax = f

13 3/14/2011ICIT-SSST'1113 Circuit Number of Scan flip- flops Number of clock rate steps Test time reduction (%) Area overhead (%) ExperimentTheory s27827.490.014.72 s38620415.2512.6415.29 s83867413.5112.6411.73 s5378263413.0312.646.65 s13207852819.0018.783.98 s359322083818.7418.782.55 s385841768818.9118.782.13 ISCAS89 Benchmark Circuits

14 S386: Activity for One Scan-In 3/14/2011ICIT-SSST'1114 Input activity = 25% Time reduction = 22.5%

15 3/14/2011ICIT-SSST'1115 Circuit Number of scan flip-flops Number of clock rate steps Test time reduction (%) u2261416846.6818.750 d28138131646.7421.810 d69582293248.2823.360 f2126155936449.1524.180 q127102615812849.4524.530 p937919691651249.7224.810 a5867104141125649.7324.770 ITC02 Benchmark Circuits

16 Improvement: Monitor Input & Output 3/14/2011ICIT-SSST'1116

17 Conclusion Dynamic control of scan clock rate reduces test time without exceeding power specification. Vectors with low average scan-in activity and high peak activity give more reduction in test time. Up to 50% reduction in test time is possible. References: P. Shanmugasundaram, Test Time Optimization in Scan Circuits, Master’s Thesis, Department of ECE, Auburn University, Auburn, Alabama, December 2010. P. Shanmugasundaram and V. D. Agrawal, “Dynamic Scan Clock Control for Test Time Reduction Maintaining Peak Power Limit,” Proc. 29 th IEEE VLSI Test Symposium, May 2-4, 2011. 3/14/2011ICIT-SSST'1117

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