1. Technion – Israel Institute of Technology Qualcomm Corp. Research and Development, San Diego, California Leveraging Application-Level Requirements in the Design of a NoC for a 4G SoC – a Case Study Rudy Beraha, Isask’har (Zigi) Walter, Israel Cidon, Avinoam Kolodny March, 2010

2. Network on-Chip (NoC)  Introduction  Design Process NoC Design  A Case Study Outline 2

3. Why Network on-Chip? Buses scale badly  Power, area, performance  Testability, verification, timing closure, … Networks are replacing system buses Low area Low power Better scalability Higher parallelism Spatial reuse Unicast 3

4. Grid topology Packet-switched XY Routing Wormhole flow-control NoC Architecture Basics Module R R R R RR R R R RRRRR RRRRR RRRRR R Router Link 4

5. Module NoC Design Flow Map modules Allocate link capacities Evaluate QoS and cost R R RRR R RRRRR RR R R R RRR R RRRRR RR RRRR RR R RR R R R R inter-module traffic Synthesize+P&R 5

6. Module R R RRR R RRRRR RR R R R R NoC Design Flow Module R R RRR R RRRRR RR R R R R Map modules Allocate link capacities Evaluate QoS and cost inter-module traffic Synthesize+P&R Goal: Design a NoC for a 4G SoC Study design alternatives 6

7. Typical modeling  Latency and dynamic power proportional to distance  Dynamic power consumed by the NoC: Why is Mapping Important? 7 Cost of mapping π

8. Example PE1PE2 PE4PE5 PE3 PE6 100 30 Mapping π 1 Mapping π 2 8

9. Network on-Chip (NoC) NoC Design – a Case Study  Mapping  Link capacity allocation  Results Outline 9

10. Approached by Qualcomm R&D  Got a real, 4G Modem SoC design to analyze! Very few NoCs for real systems are described in the literature A Case Study… 10

11. Challenge: a Bus-Based 4G SoC 11 34 Modules, ~100 flows 2 AXI buses Several modes of operation (Data, voice, data+voice, etc.)

12. Given:  Traffic pattern Optimize:  Mapping  Link capacities Synthesize+place&route Design Flow 12 Step A Step B

13. Traditional P2P traffic requirements Input Data – Traffic Pattern 13 Bandwidth demands [Mb/s]Point-to-point timing requirements [nSec] 'R' is for read operations, 'W' is for write operations

14. Minimize power subject to performance constraints Captures dynamic power and area (static power) Mapping Optimization - Goal 14 Static powerDynamic power

15. Scheme 1: Ignore timing requirements  Account for them in subsequent design phases Scheme 2: Use P2P timing requirements  Discard solutions that violate any requirement Scheme 3: Use application-level requirements Mapping Alternatives 15 New! LatencyDstSrc T1T1 CPUIO T2T2 DSPCPU T3T3 MEMDSP LatencyDstSrc T 1 + T 2 + T 3 MEMIO CPUMEMDSP

16. Assumption: latency  hop distance NP-hard  Use heuristic algorithm Simulated annealing Solving the Mapping Problem 16 Power optimized Power and point-to-point timing requirements Power and end-to-end timing requirements Scheme 1Scheme 2Scheme 3

17. Find minimal “NoC capacity” such that all timing requirements are met  Account for run-time effects finite router queues, backpressure mechanism, virtual channel multiplexing, network contention, etc.  Too much capacity: waste of resources  Too little capacity: insufficient performance Step 2: Setting Link Capacities 17

18. 18 IP1 Interface IP2 Interface More difficult than off-chip networks Cannot set link capacity independently Link Capacity and Wormhole

19. Scheme 1: Uniform link capacity  Simulation based Scheme 2: Individually tuned, heuristic-based  Simulation based Capacity Allocation Alternatives 19 Result: 12 NoCs to compare (3 mappings)*(2 allocation schemes)*(2 VC configurations)

20. Network on-Chip (NoC) NoC Design – a Case Study  Mapping  Link capacity allocation  Results Outline 20

21. Using E2E requirements during the design process reduces the total capacity  Both for uniform and non-uniform link capacity allocation Results: Total NoC Capacity 21 Total Capacity Requirements [Gbps] Scheme 3 (Power+ETE Latency) Scheme 2 (Power+P2P Latency) Scheme 1 (Power only)

22. Synthesis Results 22 Up to 49% savings! Up to 40% savings! Scheme 1Scheme 2Scheme 3 Scheme 1Scheme 2Scheme 3 Total router areaTotal wiring area Mapping scheme 1: Ignore timing requirements during mapping Mapping scheme 2: map using P2P timing requirements Mapping scheme 3: map using application-level requirements

23. Evaluated the benefit of mapping using application-level requirements  Rather than P2P constraints Using two link capacity allocation schemes Real application  Meaningful savings To do  Analyze place&route results  Compare to a bus-based implementation Conclusions and Future Work 23

24. Thank you! Questions? zigi@tx.technion.ac.il Leveraging Application-Level Requirements in the Design of a NoC QNoC Research Group Group Research QNoC 24