1. Lecture 1 Design Hierarchy Chapter 1

2. Digital System Design Flow 1.Register-Transfer Levl (RTL) – e.g. VHDL/Verilog 2.Gate Level Design 3.Circuit Level Design 4.Physical Layout

3. Verilog Include a set of 26 predefined functional models of common combinational logic gates called primitives. Primitives – The most basic functional objects that can be used to compose a design – Are built into the language by means of internal truth tables – Examples: and, nand, or, nor, xor, xnor

4. More on Primitives 3-input nand primitive – Input signal a, b, and c – Output signal y Each primitive has ports (corresponding to hardware pins and terminals) – The output port(s) of a primitive must be first in the list, followed by the primitive’s input ports.

5. Instantiated Primitives Instantiated Primitives (nor, and,nand) are connected by wires. A wire is a data-type which is used to establish connectivity in a design, just as a physical wire establishes connectivity between gates.

6. Example: a Full Adder Binary Addition Gate-Level Synthesis Verilog Representation

7. Binary Addition (1)

8. Binary Addition (2)

9. Derivation of ∑ Question: What primitive best implements ∑? Inputs: A, B Outputs: xor (∑, A, B) BA∑ 000 101 011 110

10. Derivation of Carry Out Question: What primitive best implements C o ? Inputs: A, B Outputs: and (C o, A, B) BACoCo 000 100 010 111

11. A Half Adder A half adder is useful for adding LSB.

12. Limitation of a Half Adder A half-adder does not account for carry-in.

13. Truth Table of ∑ of a Full Adder C in BA∑ 0000 0011 0101 0110 1001 1010 1100 1111 Identical to ∑ of a Half Adder C in +B+A=C in +∑ HA =C in XOR ∑ HA

14. Truth Table of C o of a Full Adder C in BACoCo 0000 0010 0100 0111 1000 1011 1101 1111 Identical to ∑ of a Half Adder Use a Half Adder with C in and ∑ HA to generate C o

15. Schematic of a Full Adder

16. A 3 bit parallel adder

17. Gate Level vs. Verilog Model of a Full Adder

18. Explanation The keywords module and endmodule encapsulate the text that describes the module The module name is Add_full Module Ports are – Input a, b, c_in – Output c_out, sum Module instances: Add_half, or

19. Nested Module Add_half is a child module of Add_full

20. Gate Level Design Basic Gates – AND, NAND,OR, NOR, XOR, XNOR,NOT Universal Gates – NAND Gates – NOR Gates Multiple Inputs Logic Gates

21. NAND Based Logic Gates

22. NOR Based Logic Gates

23. Multiple Inputs Logic Gates

24. Circuit Level

25. Physical Design Floor Planning – Estimates of the area of major units in the chip and defines their relative placements. – Estimate wire lengths and wring congestions. – Challenge: estimate the size of each unit without proceeding through a detailed design of the chip. Layout Design Verification Tapeout

26. A Sample Floor Plan λ= ½ of minimum channel length

27. A Sample Layout

28. Layout of an Inverter In a 0.6 um process 4/2=1.2 um/0.6 um.

29. Design Verification LVS (Layout vs. Schematic) checks that transistors in a layout are connected in the same way as in the circuit schematic. DRC (Design Rule Checkers) verify that the layout satisfies design rules. ERC (Electrical Rule Checkers) scan for problems such as noise or premature wearout.

30. Tapeout Tapeout gets its name from the old practice of writing a specifications of masks to a magnetic tape. GDS Foundries: – TSMC – UMC – IBM

31. Fabricated Chip

32. IC Decapsulation

33. Cross Section

34. Low Cost Package 1 12 7 Red: Top layer trace Green: Via Blue: Bottom layer trace

35. Package Parasitics