1. Addition (2)

3. Outline Full Adder 3-Bit Adder 2’s Complement Subtraction

4. A Half Adder A half adder is useful for adding LSB.

5. Limitation of a Half Adder A half-adder does not account for carry-in.

6. Derivation of the Sum Bit (∑) of a Full Adder C in ∑ half BA∑ full 00000 01011 01101 00110 10001 11010 11100 10111 A+B can be derived from the ∑ half of the half adder The sum of Cin and ∑ full can be derived from an XOR gate! Perhaps this suggests that I need another half adder!

7. Derivation of the Carryout Bit of a Full Adder Since the C o bit in a half adder is generated by an AND gate, let’s AND ∑HA and C in and see what we get!

8. Derivation of the C o bit of a Full Adder C in∙ ∑ half C in ∑ half C o,half BAC o of the full adder 0000000 0010010 0010100 0001111 0100000 1110011 1110101 0101111 C in∙ ∑ half generates partially correct Co. So far, we have not used information from the output of the half adder. So let’s use C o,half in the full adder circuit….

9. Truth Table of C o of a Full Adder C in BACoCo 0000 0010 0100 0111 1000 1011 1101 1111 Identical to ∑ of a Half Adder Use a Half Adder with C in and ∑ HA to generate C o

10. Schematic of a Full Adder

11. Derivation of the Sum Bit (∑) of a Full Adder C in BA∑ full 0000 0011 0101 0110 1001 1010 1100 1111

12. Derivation of the C o bit of a Full Adder C in BAC o of the full adder 0000 0010 0100 0111 1000 1011 1101 1111

13. A 3 bit parallel adder

14. Since it is only possible to show magnitude with a binary number, the sign (+) or (-) is shown by adding an extra “sign” bit. –A sign bit of 0 indicates a positive number. –A sign bit of 1 indicates a negative number.