1. Class Presentation on Binary Moment Diagrams by Krishna Chillara Base Paper: “Verification of Arithmetic Circuits using Binary Moment Diagrams” by Randal E. Bryant and Yirng-An Chen

2. Outline Introduction Binary Moment Diagrams (BMDs) MTBDDs, BMDs
*BMDs - Illustration
Construction rules of *BMDs
Boolean functions using *BMDs
Word level Operations using *BMDs
Verification using *BMDs
Summary

3. Introduction Some function representations discussed in this course
Sum of the Product form
Factored forms
Truth Table
Binary Decision Diagrams
Simple in representing and manipulating Boolean functions
Reduced Ordered BDDs are canonical (useful for verification)
Drawbacks of BDDs
Does not handle functions with non-Boolean range
Bit level representation but specs are in word level
Not good in terms of memory for multiplications
Consider a 32 bit multiplication using BDDs
M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

4. Shannon Expansion
Boolean function f decomposed in terms of a variable x can be represented by Shannon expansion as
f = x fx + x’ fx’
Function decomposed into positive and negative co-factors at the node variable x
fx = f(x=1)
fx ’ = f(x=0)
Point-wise decomposition

5. Binary Moment Diagrams (BMDs)
Modified Shannon Expansion
Boolean variable treated as a binary (0,1) integer variable
Complement of x modeled as (1-x)
Now the function can be represented as
f = x fx + x’ fx’
= x fx + (1-x) fx’
= fx’ + x (fx - fx’ )
= fx’ + x fx
Function is branched into two components
Constant Component (Negative co-factor)
Linear Component
Comparison with shannon expansion for Boolean
M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

6. Binary Moment Diagrams (BMDs) from truth table
For variable y,
y = 1 is encoded as y
y = 0 is encoded as (1-y)
With this encoding, linear expression can be directly obtained from the truth table
Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

7. Representation with MTBDDs and BMDs
Multi Terminal BDDs
Extending BDDs to allow numeric leaf values
Point-wise decomposition based on Shannon expansion
BMDs
Linear moment decomposition
Dotted node represents constant moment and solid line represents linear moment
Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

8. Multiplicative BMDs (*BMDs)
BMDs simply encode the numerical values into terminal vertices.
In *BMDs edge weights are used to share any common sub-expressions.
*BMDs
Not decision diagrams as they are based on the moment decomposition
Multiplicative diagrams – each path is a product of nodes and the edge weights
Function is evaluated by adding all the encoded paths like in BDDs

9. BMD reduction rules Irredundancy Merge the duplicates
When a linear moment of at a node v is 0, the function has only a constant term and thus does not depend on ‘v’.
Hence node ‘v’ can be removed.
Merge the duplicates
Similar to BDDs
Two nodes with same index variable and having same two moments can be merged.
M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

10. Normalization of weights
Rules imposed on manipulating edge weights to make the graph canonical
Normalized by factoring out gcd of the argument weights w=gcd(wl(x),wh(x))
Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

11. Illustration
f=8-20z+2y+4yz+12x+24xz+15xy
Variable order (say) x,y,z
f= fx’ + x fx
Linear = fx
Constant = fx’ x
8+2y+4yz-20z
12+15y+24z y y
8-20z
12+24z
4z+2 z z z 8
-20 2 4 12 24 15

12. Illustration x y y z z z 2 -5 1 2 1 2 5 f=8-20z+2y+4yz+12x+24xz+15xy
Variable order (say) x,y,z
Introducing the edge weights x
8+2y+4yz-20z
12+15y+24z 2 3
4+y+2yz-10z y
4+5y+8z y
4-10z
8z+4 2 4
2-5z
2z+1
2z+1 z z z 2 -5 1 2 1 2 5

13. Illustration x y y z z 1 f=8-20z+2y+4yz+12x+24xz+15xy
= 8-20z+2y (1+2z) + 12x(1+2z) +15xy
Variable order (say) x,y,z
*BMD after reduction x 2 3
4+y+2yz-10z y
4+5y+8z y 2 4
2-5z 5 z z
2z+1 2 -5 2 1

14. Illustration BMD and *BMD
Unsigned integer: X = 8x3 + 4x2 + 2x1 + x0 x3 8 x2 x1 x0 4 2 1
BMD 1 x0 x1 x2 2 4 x3 8
*BMD
Slide taken from Prof. Ciesielski’s TED presentation.

15. Representation of Integers
Unsigned – sum of the weighted bits
Signed – Two’s complement, Sign-Magnitude
Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

16. Representation of Boolean Logic
NOT : x’ = (1-x)
AND: x.y
OR: x+y-(x.y)
XOR: x+y-2(x.y) x x x x y y y y y -1 -1 -2 1 1 1 1
NOT
AND OR
XOR
M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

17. Representation of word level operations - Addition
SUM X+Y
Both X and Y here are 3 bit wide
X= 4x2+2x1+x0 Y= 4y2+2y1+y0
X+Y = (4x2+2x1+x0)+(4y2+2y1+y0)
= 4*(x2 +y2) + 2*(x1 +y1) + (x0 +y0)
Linear with n- #bits
Why is it called word level?
Bit level vs word level in *BMDs - example x2 y2 4 x1 4 y1 2 2 x0 1 y0 1 1
M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

18. Bit level representation of addition
Derived using gate level representation of the circuit
Sum using XORs and carry using AND, OR gates
Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

19. Representation of word level operations - Product
Product X*Y
Both X and Y here are 3 bit wide
X= 4x2+2x1+x0 Y= 4y2+2y1+y0
X*Y = (4x2+2x1+x0)*(4y2+2y1+y0)
= 4x2 *(4y2+2y1+y0) + 2x1 *(4y2+2y1+y0) x0*(4y2+2y1+y0)
Variable order x2x1x0y2y1y0
Linear with n- #bits x2 x1 4 x0 2 1 y2 4 y1 2 y0 1 1
M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

20. Verification Problem
Goal: To prove equivalence between the bit level circuit and word level specification
Circuit output interpreted as word should match the specification when applied to word level interpretations of the input
Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

21. Hierarchical verification using *BMDs
*BMDs can represent both bit level and word level functions efficiently
Circuit partitioned into component modules based on word level structures
Each component verified against the word level specification
Word level functions are composed and compared to overall circuit specification
Addition
Compute P using the bitwise *BMD results
Compare the *BMD for P with the word level representation of X+Y

22. Hierarchical verification using *BMDs
Multiplication
Circuits like multipliers cannot be verified efficiently at bit level (why?)
Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

23. Hierarchical verification using *BMDs
Each box (i,j) represents a cell containing an AND gate to form the partial product and a Full Adder (FA) to add this bit to the product
Vertical rectangles indicate the word level partitioning of the circuit
Add Stepi has
input multiplicand word X
One bit multiplier yi
Partial sum input word Pi
Generates a output word Po using
Verification involves
Checking each component
Composition of word level functions matching integer multiplication

24. Results
Number of multiplier circuits with different word sizes are used (16 bit, 64 bit and 256 bit)
Metrics – CPU minutes and memory
Maximum 33 min on 256 bit word and 14.4 MB of memory
Can verify circuits with upto 256 bit word sizes requiring 653,056 logic gates
Ochi et. al verified successfully 15 bit word size using 12 million vertices
Increasing one bit increases number of vertices by 2.7
Jain et al used Indexed BDDs to verify multipliers
It took almost 4 hours of CPU time
Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

25. Summary *BMDs for mapping Boolean variables to numeric values
Construction of *BMDs
reduction rules
Normalization
Representing Boolean logic
Word level
Hierarchical verification
Component verification
Word level comparison

26. References
[1] Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995
[2] M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification

27. Thank You!