1. CSE 490/590, Spring 2011 CSE 490/590 Computer Architecture ISAs and MIPS Steve Ko Computer Sciences and Engineering University at Buffalo

2. CSE 490/590, Spring 2011 2 Last Time… Computer Architecture >> ISAs and RTL Comp. Arch. shaped by technology and applications Computer Architecture brings a quantitative approach to the table –5 quantitative principles of design The current performance trend shows that –Latency lags behind bandwidth

3. CSE 490/590, Spring 2011 Instruction Set Architecture (ISA) The contract between software and hardware Typically described by giving all the programmer- visible state (registers + memory) plus the semantics of the instructions that operate on that state IBM 360 was first line of machines to separate ISA from implementation (aka. microarchitecture) Many implementations possible for a given ISA –E.g., today you can buy AMD or Intel processors that run the x86- 64 ISA. –E.g.2: many cellphones use the ARM ISA with implementations from many different companies including TI, Qualcomm, Samsung, Marvell, etc. –E.g.3., the Soviets build code-compatible clones of the IBM360, as did Amdhal after he left IBM. 3

4. CSE 490/590, Spring 2011 4 ISA to Microarchitecture Mapping ISA often designed with particular microarchitectural style in mind, e.g., –CISC  microcoded –RISC  hardwired, pipelined –VLIW  fixed-latency in-order parallel pipelines –JVM  software interpretation But can be implemented with any microarchitectural style –Intel Nehalem: hardwired pipelined CISC (x86) machine (with some microcode support) –Intel could implement a dynamically scheduled out- of-order VLIW Itanium (IA-64) processor –ARM Jazelle: A hardware JVM processor

5. CSE 490/590, Spring 2011 5 Datapath vs Control Datapath: Storage, FU, interconnect sufficient to perform the desired functions –Inputs are Control Points –Outputs are signals Controller: State machine to orchestrate operation on the data path –Based on desired function and signals Datapath Controller Control Points signals

6. CSE 490/590, Spring 2011 6 Microcoded Microarchitecture (CISC) Memory (RAM) Datapath controller (ROM) AddrData zero? busy? opcode enMem MemWrt holds fixed microcode instructions holds user program written in macrocode instructions (e.g., MIPS, x86, etc.)

7. CSE 490/590, Spring 2011 Inst 3 CISC 7 7 cycles Inst 1Inst 2 5 cycles10 cycles Time Variable cycles per instruction Variable address modes reg-reg, reg-mem, mem-mem, etc. Convenient for programmers Support many instructions Difficult to predict completion time No good for pipelining

8. CSE 490/590, Spring 2011 8 Hardwired Control is pure Combinational Logic (RISC) combinational logic op code zero? ExtSel BSrc OpSel MemWrite WBSrc RegDst RegWrite PCSrc

9. CSE 490/590, Spring 2011 9 A "Typical" RISC ISA 32-bit fixed format instruction (3 formats) 32 32-bit GPR (R0 contains zero, DP take pair) 3-address, reg-reg arithmetic instruction Single address mode for load/store: base + displacement –no indirection Simple branch conditions Delayed branch Designed for use by compilers & pipelining see: SPARC, MIPS, HP PA-Risc, DEC Alpha, IBM PowerPC, CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3

10. CSE 490/590, Spring 2011 10 Example: MIPS Op 312601516202125 Rs1Rd immediate Op 3126025 Op 312601516202125 Rs1Rs2 target RdOpx Register-Register 56 1011 Register-Immediate Op 312601516202125 Rs1Rs2/Opx immediate Branch Jump / Call

11. CSE 490/590, Spring 2011 Hardware Elements Combinational circuits –Mux, Decoder, ALU,... Synchronous state elements –Flipflop, Register, Register file, SRAM, DRAM Edge-triggered: Data is sampled at the rising edge Clk D Q En ff Q D Clk En OpSelect - Add, Sub,... - And, Or, Xor, Not,... - GT, LT, EQ, Zero,... Result Comp? A B ALU Sel O A 0 A 1 A n-1 Mux... lg(n) A Decoder... O 0 O 1 O n-1 lg(n)

12. CSE 490/590, Spring 2011 12 Register Files ReadData1 ReadSel1 ReadSel2 WriteSel Register file 2R+1W ReadData2 WriteData WEClock rd1 rs1 rs2 ws wd rd2 we Reads are combinational ff Q0Q0 D0D0 Clk En ff Q1Q1 D1D1 Q2Q2 D2D2 Q n-1 D n-1... register

13. CSE 490/590, Spring 2011 13 A Simple Memory Model MAGIC RAM ReadData WriteData Address WriteEnable Clock Reads and writes are always completed in one cycle a Read can be done any time (i.e. combinational) a Write is performed at the rising clock edge if it is enabled  the write address and data must be stable at the clock edge

14. CSE 490/590, Spring 2011 14 CSE 490/590 Administrivia Please check the web page: http://www.cse.buffalo.edu/~stevko/courses/cse4 90/spring11 http://www.cse.buffalo.edu/~stevko/courses/cse4 90/spring11 Don’t forget –Recitations start from this week. –Please purchase a BASYS2 board (100K) as soon as possible. –Projects should be done individually. Please read the syllabus webpage. I have no idea how fast/slow I’m going. –Please stop me if too fast!

15. CSE 490/590, Spring 2011 15 Implementing MIPS: Single-cycle per instruction datapath & control logic

16. CSE 490/590, Spring 2011 16 The MIPS ISA Processor State 32 32-bit GPRs, R0 always contains a 0 32 single precision FPRs, may also be viewed as 16 double precision FPRs FP status register, used for FP compares & exceptions PC, the program counter some other special registers Data types 8-bit byte, 16-bit half word 32-bit word for integers 32-bit word for single precision floating point 64-bit word for double precision floating point Load/Store style instruction set data addressing modes- immediate & indexed branch addressing modes- PC relative & register indirect Byte addressable memory- big endian mode All instructions are 32 bits

17. CSE 490/590, Spring 2011 17 Example: MIPS Op 312601516202125 Rs1Rd immediate Op 3126025 Op 312601516202125 Rs1Rs2 target RdOpx Register-Register 56 1011 Register-Immediate Op 312601516202125 Rs1Rs2/Opx immediate Branch Jump / Call

18. CSE 490/590, Spring 2011 18 Instruction Execution Execution of an instruction involves 1. instruction fetch 2. decode and register fetch 3. ALU operation 4. memory operation (optional) 5. write back and the computation of the address of the next instruction

19. CSE 490/590, Spring 2011 19 Datapath: Reg-Reg ALU Instructions RegWrite Timing? 6 5 5 5 5 6 0 rsrt rd 0 func rd  (rs) func (rt) 31 26 25 21 20 16 15 11 5 0 0x4 Add clk addr inst Inst. Memory PC inst OpCode z ALU Control RegWrite clk rd1 GPRs rs1 rs2 ws wd rd2 we

20. CSE 490/590, Spring 2011 20 Datapath: Reg-Imm ALU Instructions 6 5 5 16 opcode rsrt immediate rt  (rs) op immediate 31 26 25 2120 16 15 0 Imm Ext ExtSel inst OpCode 0x4 Add clk addr inst Inst. Memory PC z ALU RegWrite clk rd1 GPRs rs1 rs2 ws wd rd2 we inst ALU Control

21. CSE 490/590, Spring 2011 21 Conflicts in Merging Datapath Imm Ext ExtSel OpCode 0x4 Add clk addr inst Inst. Memory PC z ALU RegWrite clk rd1 GPRs rs1 rs2 ws wd rd2 we inst ALU Control inst opcode rsrt immediate rt  (rs) op immediate 6 5 5 5 5 6 0 rsrt rd 0 func rd  (rs) func (rt) Introduce muxes

22. CSE 490/590, Spring 2011 22 Datapath for ALU Instructions, opcode rsrt immediate rt  (rs) op immediate 6 5 5 5 5 6 0 rsrt rd 0 func rd  (rs) func (rt) BSrc Reg / Imm RegDst rt / rd Imm Ext ExtSel OpCode 0x4 Add clk addr inst Inst. Memory PC z ALU RegWrite clk rd1 GPRs rs1 rs2 ws wd rd2 we OpSel ALU Control

23. CSE 490/590, Spring 2011 23 Datapath for Memory Instructions Should program and data memory be separate? Harvard style: separate (Aiken and Mark 1 influence) - read-only program memory - read/write data memory - Note: Somehow there must be a way to load the program memory Princeton style: the same (von Neumann’s influence) - single read/write memory for program and data - Note: A Load or Store instruction requires accessing the memory more than once during its execution

24. CSE 490/590, Spring 2011 24 Load/Store Instructions: Harvard Datapath WBSrc ALU / Mem rs is the base register rt is the destination of a Load or the source for a Store 6 55 16 addressing mode opcode rsrt displacement (rs) + displacement 31 26 25 21 20 16 15 0 RegDst BSrc “base” disp ExtSelOpCodeOpSel ALU Control z ALU 0x4 Add clk addr inst Inst. Memory PC RegWrite clk rd1 GPRs rs1 rs2 ws wd rd2 we Imm Ext clk MemWrite addr wdata rdata Data Memory we

25. CSE 490/590, Spring 2011 25 MIPS Control Instructions Conditional (on GPR) PC-relative branch Unconditional register-indirect jumps Unconditional absolute jumps PC-relative branches add offset4 to PC+4 to calculate the target address (offset is in words): 128 KB range Absolute jumps append target4 to PC to calculate the target address: 256 MB range jump-&-link stores PC+4 into the link register (R31) All Control Transfers are delayed by 1 instruction we will worry about the branch delay slot later 6 55 16 opcode rs offset BEQZ, BNEZ 6 26 opcode targetJ, JAL 6 55 16 opcode rsJR, JALR

26. CSE 490/590, Spring 2011 26 Conditional Branches (BEQZ, BNEZ) 0x4 Add PCSrc clk WBSrcMemWrite addr wdata rdata Data Memory we RegDst BSrc ExtSelOpCode z OpSel clk zero? clk addr inst Inst. Memory PC rd1 GPRs rs1 rs2 ws wd rd2 we Imm Ext ALU Control Add br pc+4 RegWrite

27. CSE 490/590, Spring 2011 27 Register-Indirect Jumps (JR) 0x4 RegWrite Add clk WBSrcMemWrite addr wdata rdata Data Memory we RegDst BSrc ExtSelOpCode z OpSel clk zero? clk addr inst Inst. Memory PC rd1 GPRs rs1 rs2 ws wd rd2 we Imm Ext ALU Control PCSrc br pc+4 rind

28. CSE 490/590, Spring 2011 28 Register-Indirect Jump-&-Link (JALR) 0x4 RegWrite Add clk WBSrcMemWrite addr wdata rdata Data Memory we RegDst BSrc ExtSelOpCode z OpSel clk zero? clk addr inst Inst. Memory PC rd1 GPRs rs1 rs2 ws wd rd2 we Imm Ext ALU Control 31 PCSrc br pc+4 rind

29. CSE 490/590, Spring 2011 29 Absolute Jumps (J, JAL) 0x4 RegWrite Add clk WBSrcMemWrite addr wdata rdata Data Memory we RegDst BSrc ExtSelOpCode z OpSel clk zero? clk addr inst Inst. Memory PC rd1 GPRs rs1 rs2 ws wd rd2 we Imm Ext ALU Control 31 PCSrc br pc+4 rind jabs

30. CSE 490/590, Spring 2011 30 Harvard-Style Datapath for MIPS 0x4 RegWrite Add clk WBSrcMemWrite addr wdata rdata Data Memory we RegDst BSrc ExtSelOpCode z OpSel clk zero? clk addr inst Inst. Memory PC rd1 GPRs rs1 rs2 ws wd rd2 we Imm Ext ALU Control 31 PCSrc br rind jabs pc+4

31. CSE 490/590, Spring 2011 31 Single-Cycle Hardwired Control: Harvard architecture We will assume clock period is sufficiently long for all of the following steps to be “completed”: 1. instruction fetch 2. decode and register fetch 3. ALU operation 4. data fetch if required 5. register write-back setup time   t C > t IFetch + t RFetch + t ALU + t DMem + t RWB At the rising edge of the following clock, the PC, the register file and the memory are updated

32. CSE 490/590, Spring 2011 32 An Ideal Pipeline All objects go through the same stages No sharing of resources between any two stages Propagation delay through all pipeline stages is equal The scheduling of an object entering the pipeline is not affected by the objects in other stages stage 1 stage 2 stage 3 stage 4 These conditions generally hold for industrial assembly lines. But can an instruction pipeline satisfy the last condition?

33. CSE 490/590, Spring 2011 33 Acknowledgements These slides heavily contain material developed and copyright by –Krste Asanovic (MIT/UCB) –David Patterson (UCB) And also by: –Arvind (MIT) –Joel Emer (Intel/MIT) –James Hoe (CMU) –John Kubiatowicz (UCB) MIT material derived from course 6.823 UCB material derived from course CS252