1. ECE 667 Student Presentation Gayatri Prabhu [1]. *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification – Y. Chen, R. Bryant, ICCAD 1997 *PHDD: Multiplicative Power Hybrid Decision Diagrams [1] 1

2. 2 Agenda  Motivation  Floating point representation  *PHDD construction  Floating point function through *PHDDs  Benefits  Conclusion

3. 3 Motivation  BMDs [1], *BMDs [1],K*BMDs [2] and HDDs [3] inefficient to map Boolean vectors to floating point values. Output in the form of a word. Need some way of incorporating the radix point Need rational number (n/d) representation Computationally expensive  Extend *BMDs to *PHDDs [1] Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995 [2] Drechsler R., Becker,B. and Ruppertz,S. “K*BMDs: a new data structure for verification”, DATE 1995 [3] Clarke, E.M, Fujita M, Zhao X. “Hybrid decision diagrams overcoming the limitations of MTBDDs and BMDs “, ICCAD 1995

4. 4 Floating point representation  Floating point : Radix point at an arbitrary position  IEEE 754 notation to store in memory Derived from scientific notation Eg : 123.45 = 1.2345 x 10 2 Number = (-1) sign x (Base) exponent x Mantissa  Sign: 0 means positive and 1 means negative  Base = 2 SignEM nm http://steve.hollasch.net/cgindex/coding/ieeefloat.html

5. 5 Floating point representation  Mantissa - m bits Radix point after first non-zero digit; Base 2 => Non zero-digit =1 Mantissa always in form 1.M ; Stored mantissa = M  Exponent – n bits Stored exponent = Actual exponent + Bias Bias to remove negative numbers in the stored format For n-bit exponent bias = 2 n-1 -1  So for n =3, m = 3; Bias = 2 (3-1) - 1 ; 0.75 = 0.11 Sign=0; Stored exponent = -1+3 =2 ; Stored mantissa = 0b100 5 = 5.00 x 10 0 5 = 5000.0 x 10 -3

6. 6 Floating point representation  Number = (-1) s x 2 (E-bias) x 1.M Normal form  Overflow : Exponent requires more bits Not considered in *PHDDs  Underflow : Number too small to represent with precision. Eg:0.000000000000075 Need to approximate to zero Denormal form : (-1) s x 2 (1-bias) x 0.M

7. 7 Failure of BMDs and *BMDs to represent floats 2 X-2 1 3 x1x1 x0x0 1/4 1 3 2X2X x1x1 x0x0 x0x0 x0x0 1248 x1x1 2X2X x0x0 x0x0 1/2 12 x1x1 2 X-2 “ *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification “ Y. Chen, R. Bryant, ICCAD 1997

8. 8 *PHDDs : Construction and manipulation

9. 9 *PHDD- Introduction  Multiplicative Power Hybrid Decision Diagrams Multiplicative Edge weights multiplied with variables Power Edge weights restricted to powers of a constant Hybrid since different decompositions allowed Shannon - Positive Davio - Negative Davio

10. 10 Edge Weight rules  Edge Weights = w which represents c w ; c a constant ; positive w can be positive or negative Only c=2 considered since the effort is directed towards floating point arithmetic.  All edges have weight; No weights near edge=> w=0 Represented function = {2 0 x 0 +2 1 x 1 +2 2 x 2 } 0 1 x0x0 x1x1 x2x2 2 1 “ *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification “ Y. Chen, R. Bryant, ICCAD 1997

11. 11 *PHDDs Reduction rules (1)  Normalize edge weights Atmost one branch has non-zero weight Edge weights ≥ 0 except for the top one Leaf nodes can have only odd integers or 0. “ *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification “ Y. Chen, R. Bryant, ICCAD 1997

12. 12 *PHDDs Reduction rules (2)  Introduce negation edges Increases sharing Helpful whenever a sign bit is involved 1 x3x3 0 1 x0x0 x1x1 x2x2 2 1 0 x0x0 x1x1 x2x2 2 1 1 x3x3 0 1 x0x0 x1x1 x2x2 2 1 “ *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification “ Y. Chen, R. Bryant, ICCAD 1997

13. 13 Decomposition One variable always associated with one type of decomposition f= 1+y+3x+3xy “ *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification “ Y. Chen, R. Bryant, ICCAD 1997

14. 14 Making *PHDDs canonical  Follow ordering  Associate decomposition type with variable  Remove redundancy  Merge duplicates  Normalize edge weights  Negation edges whenever necessary  Zero edge of every node is a regular edge  Negation of leaf 0 is still leaf 0  Leaves must be non-negative

15. 15 *BMD vs *PHDD *BMDs  Decomposition - Positive Davio  Edge weight – any number  Weight manipulation - requires GCD computations *PHDDs  Decomposition – Shannon, Positive Davio & Negative Davio  Edge weight – Powers of 2 (exponents)  Weight manipulation – just addition and subtraction

16. 16 Representing a function in *PHDD x1x1 x0x0 f 001 012 104 118 x0x0 x0x0 12 48 x1x1 2X2X HDD representation with Shannon decomposition x 1, x 0 bits of a number => X= x 0 +2x 1 and f = 2 X “ *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification “ Y. Chen, R. Bryant, ICCAD 1997

17. 17 Conversion from HDD to *PHDD x0x0 x0x0 12 48 x1x1 2X2X x0x0 x0x0 1 23 x1x1 2X2X 1 x0x0 x0x0 1 2 1 x1x1 2X2X 1 x1x1 2 x0x0 1 1 2X2X Extract powers of 2 Normalize Reduce “ *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification “ Y. Chen, R. Bryant, ICCAD 1997

18. 18 Manipulating *PHDDs -2 2 X-2 x1x1 2 x0x0 1 1 x1x1 2 x0x0 1 1 2X2X “ *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification “ Y. Chen, R. Bryant, ICCAD 1997 Represent c X where X is a number and c=2 2 x0x0 1 1 x1x1 2 X 1 More bit in X x2x2 3

19. 19 *PHDDs and ARITHMETIC

20. 20 Floating point operations  Break down into sign, exponent and mantissa part  PHDDs for each part Shannon for sign Shannon for exponent Positive Davio for mantissa  Combine all the individual parts Bias at the top followed by sign, exponent and mantissa

21. 21 ex 1 ex 0 1 2 Floating Point Encoding Functions:(-1) Sx * 2 (EX-Bias) * 1.X – Exponent: 2bits, Mantissa: 3bits, Bias:1 1 Sx ex 1 2 ex 0 1 1 -3-4 Sx -4 3 1 x0x0 x1x1 x2x2 2 1 0 1 x0x0 x1x1 x2x2 2 1 -3 0 1 x0x0 x1x1 x2x2 2 1 “ *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification “ Y. Chen, R. Bryant, ICCAD 1997

22. 22 PHDDs and floating point encoding Normal ->(-1) S * 2 (EX-Bias) * 1.M Denormal ->(-1) S * 2 (1-Bias) * 0.M EX – 3 bits ; X – 4 bits ; B =3 “ *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification “ Y. Chen, R. Bryant, ICCAD 1997

23. 23 Applying *PHDDs to arithmetic operations 1.Represent numbers in a binary encoded form 2.Use composition (~ APPLY in BDDs) to combine the numbers in operations 1.Eg: Floating point multiplication

24. 24 Floating point multiplication “ *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification “ Y. Chen, R. Bryant, ICCAD 1997

25. 25 Advantages and disadvantages  Advantages Six times faster than *BMDs Uses less memory Linear complexity for FP multiplication  Disadvantages Edge weights restricted to powers of 2 Floating point addition complexity exponential with exponent size  Applications Floating point circuit verification

26. 26 Conclusion  *PHDDs mainly for floating point verification  Edge weights power of 2  Reduction rules  Boolean to Floating point : Shannon decomposition for sign and exponent; Positive Davio for Mantissa  Boolean to Integers : Positive Davio decomposition  Boolean to Boolean : Shannon decomposition

27. 27

28. 28 Backup

29. 29 Sign bit --- Actually a form of decision making x f Y Z

30. 30 Integer representation of a 3-bit number 1 x3x3 0 1 x0x0 x1x1 x2x2 2 1 “ *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification “ Y. Chen, R. Bryant, ICCAD 1997 3 x3x3 0 1 x0x0 x1x1 x2x2 2 1 Unsigned Sign Magnitude Twos complement Sign : Shannon Mag. : Davio

31. 31 Integer operations Addition : Summing weighted bits x i +y i Multiplication: Summing weighted partial products … X = 1 1 0 Y=1 1 1 Y*X = (x i Y) 2 i = (x i 2 i ) Y 1 1 1 * 1 1 0 ----------- 0 0 0 1 1 1 0 1 1 1 0 0 “ *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification “ Y. Chen, R. Bryant, ICCAD 1997

32. 32 Complexity of FP Addition Operands: – F x =(-1) Sx * 1.X * 2 EX – F y =(-1) Sy * 1.Y * 2 EY – Assume EX >=EY – k=EX-EY (-1) Sx *1.X R= (-1) Sx *1.X + (-1) Sy *(1.Y >>k)) (-1) Sy * 1.Y + k Exact Result – Fx+Fy= 2 EX * ((-1) Sx * 1.X + (-1) Sy * (1.Y >>k)) Complexity: – 2 n -2 possible values for k. – O(2 n ) “ *PHDD: An Efficient Graph Representation for Floating Point Circuit Verification “ Y. Chen, R. Bryant, ICCAD 1997

33. 33 Negation edges

34. 34 Decomposition  Shannon  Positive Davio  Negative Davio