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M. Ruiz et al. 1 Real time plasma disruptions detection in JET implemented with the ITMS platform using FPGA based IDAQ J. Nieto on behalf of M. Ruiz 1,

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Presentation on theme: "M. Ruiz et al. 1 Real time plasma disruptions detection in JET implemented with the ITMS platform using FPGA based IDAQ J. Nieto on behalf of M. Ruiz 1,"— Presentation transcript:

1 M. Ruiz et al. 1 Real time plasma disruptions detection in JET implemented with the ITMS platform using FPGA based IDAQ J. Nieto on behalf of M. Ruiz 1, J. Vega 2, G. Ratta 2, E. Barrera 1, A. Murari 3, R. Meléndez 1, and JET EFDA contributors 1 Universidad Politécnica de Madrid 2 Asociación EURATOM/CIEMAT para Fusión 3 Consorzio RFX – Associazione EURATOM ENEA per la Fusione

2 M. Ruiz et al. 2 Objectives and methodology  To implement in real time a pattern recognition algorithm for disruption detection using commercial platforms based in PXI and PXIe.  To use FPGA based DAQ cards (intelligent data acquisition) for implementing the real time disruption detection (RTDD) system. 1. MATLAB implementation Algorithms were developed in MATLAB, using floating point representation, based in JET discharges files and pattern recognition techniques. 2. LabVIEW PC Migration of MATLAB code to LabVIEW using floating point representation Performance measurement in a PC (LabVIEW profiling) Simulation of floating point to fixed point algorithm transformation 3. LabVIEW & LabVIEW/FPGA Synthesis with LabVIEW/FPGA and XST Code optimization. Final test and comparisons. 4. System Integration in PXIe platform Implementation of signal generation Implementation of HOST SW

3 M. Ruiz et al. 3Implementation Signal generation IDAQ

4 M. Ruiz et al. 4 Implementation & Conclusions IDAQ implements FFT analysis and spectral deviation. –Total Slices: 61.6% (11820 out of 19200) –Flip Flops: 45.2% (8669 out of 19200) –Total LUTs: 55.2% (10595 out of 19200) –DSP48Es: 68.8% (22 out of 32) –Block RAMs: 34.4% (11 out of 32) SCPU executes the hyper-plane distance computation (CPU load less than 3%). Algorithm implemented in the FPGA

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