1. Page 1 98 學年度 ( 上 ) Final Project You can choose either 16-channelgate driver circuit (1) 16-channel gate driver circuit or 2-bit 6-channelsource driver (2) 2-bit 6-channel source driver as your final project 評分標準 :(1)gate driver :70~90 (2)source driver:80~100

2. Page 2 98 學年度 ( 上 ) Flat Panel Display : Principle and Driving Circuit Design 16-channelgate driver circuit Final Project (1) – 16-channel gate driver circuit Design a 16-channel gate driver circuit for TFT-LCD Please use the level shifter shown in next page. Use H-SPICE with 0.35um model ‘l35uhv12v’ Use a 5-level RC load (R=2KΩ, C=25pF) You must finish a final report in power point or Word form before 99/1/14 (17:00) and mail to the teacher.

3. Page 3 98 學年度 ( 上 ) Level Shifter Vin=0~Vcc –Vcc=3.0V Vout=0~AVdd –AVdd=12V

4. Page 4 98 學年度 ( 上 ) Function block of gate driver Function block of gate driver circuit 16-bit Shift register Level Shifter Buffer (Inverter) Load CLK STP Reset Vout

5. Page 5 98 學年度 ( 上 ) Load 5-level RC load 2K 25pF Vout1 1-channel Gate Driver Circuit Vout2

6. Page 6 98 學年度 ( 上 ) Flat Panel Display : Principle and Driving Circuit Design  The project must include: Schematics (gate level) of all block SPICE netlist file Timing diagram  Vout1, Vout2 & All Control Signals  Rising/falling times Find current consumption – i(Vcc) & i(Vdda) and I ave (Vcc) & I ave (Vdda) for digital and analog circuits, respectively. Find total power consumption (instaneous and average). Discussions ( and what you have learned ) References

7. Page 7 98 學年度 ( 上 ) Notice If you have any problem, please e-mail to me or call 0935-761741.

8. Page 8 98 學年度 ( 上 ) Flat Panel Display : Principle and Driving Circuit Design 2-bit 6-channelsource driver Final Project (2) – 2-bit 6-channel source driver 1 persons in a group Design a 2-bit 6-channel source driver for TFT-LCD Source driver circuits are based on your homework 1~3 Use Nanosim/Powermill or H-SPICE with 0.35um model ‘l35uhv12v’ Use a 5-level RC load (R=2KΩ, C=25pF) You must finish a final report in power point or Word form before 99/1/14 (17:00) and mail to the teacher.

9. Page 9 98 學年度 ( 上 ) Flat Panel Display : Principle and Driving Circuit Design  The project must include: Schematics (gate level) of all block (see next page) SPICE file Timing diagram  Vin & All Control Signals & Vout ： Vin ： 2-bit for each R 、 G 、 B (see page 4~5)  Rising/falling/settling(rise & fall) times  Offset voltages for each level Find current consumption – i(Vcc) & i(Vdda) and I ave (Vcc) & I ave (Vdda) for digital and analog circuits, respectively. Find total power consumption (instaneous and average). Discussions ( and what you have learned ) References

10. Page 10 98 學年度 ( 上 ) Block Diagram of Source Driver IC OUT[1] DIO1 DIO2 V GAMMA [1-4] R[1-2] G[1-2] B[1-2] CLK (SHL) POL CLK1 (EQC) Analog (LS, DAC, Buffer) Vcc/gnd OUT[2] OUT[3] OUT[4] OUT[5] OUT[6] Vdda/Agnd 6 bit Digital (SR, Latch1&2)

11. Page 11 98 學年度 ( 上 ) Input Data 2-bit x R 、 G 、 B data input (6-bit) –Red : level 0  1  2  3… –Green : level 1  2  3  0… –Blue : level 2  3  0  1… Please run at least 6 clock cycles Clock frequency = 100 KHz Please use “dot inversion”

12. Page 12 98 學年度 ( 上 ) Timing of Input Data Data CLK DIO1 6 CLKs Invalid Valid DIO2 6 Outputs for 1~2 Pixel P1P2P3P4P5P6

13. Page 13 98 學年度 ( 上 ) Digital Circuit Block Shift Register and Latch SR-1SR-2 DIO1DIO2 Latch 1 (6x2 bit) Latch 2 (6x2 bit) Vdata Ctrl ‘Ctrl’ is generated from ‘CLK1’ 6 bit CLK

14. Page 14 98 學年度 ( 上 ) Analog Circuit Block ACELL SW-P SW-N LVSH (EQC)POLVpos,ref[1-2] D1[0:1] D2[0:1] D3[0:1] D4[0:1] OUT1 OUT2 OUT3 OUT4 Vneg,ref[1-2]CLK1 OP SW-P SW-N LVSH D5[0:1] D6[0:1] OUT5 OUT6 OP SW-P

15. Page 15 98 學年度 ( 上 ) Level Shifter Vin=0~3V –Vcc=3V Vout=0~12V –AVdd=12V

16. Page 16 98 學年度 ( 上 ) Load 2K 25pF Vout1 Source Driver Circuit Vout2

17. Page 17 98 學年度 ( 上 ) V Gamma for DAC For negative polarity ： Vgamma[1]=0.5V ， Vgamma[2]=5.0V ； negative polarity is from 0.5 to 5V, 4 level, step 1.5V ； For positive polarity ： Vgamma[3]=7V ， Vgamma[4]=11.5V ； positive polarity is from 7 to 11.5V, 4 level, step 1.5V ；

18. Page 18 98 學年度 ( 上 ) Timing Diagram of Output LD is generated from CLK1

19. Page 19 98 學年度 ( 上 ) Notice If you have any problem, please e-mail to me or call 0935-761741.