1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 425 - VLSI Circuit Design Lecture 25 - Subsystem Design (cont’d) Spring 2007

2. ECE 425 Spring 2007Lecture 25 - Subsystem Design2 Announcements  No Final Exam  Reading  Wolf: 6.1-6.9  These notes drawn in part from handouts by  J. Rabaey, Digital Integrated Circuits, © Prentice-Hall 1995.

3. ECE 425 Spring 2007Lecture 25 - Subsystem Design3 Where We Are:  Last Time:  Custom Subsystem Design - Multipliers  Today:  Custom Subsystem Design - Memories / Structured Logic

4. ECE 425 Spring 2007Lecture 25 - Subsystem Design4 Subsystem Design  General Techniques  Pipelining  Datapath Design  Common Subsystems  Shifters  Adders  ALUs  Multipliers  Memories   Structured Logic

5. ECE 425 Spring 2007Lecture 25 - Subsystem Design5 Memory Classification

6. ECE 425 Spring 2007Lecture 25 - Subsystem Design6 Memory Architecture - Decoders

7. ECE 425 Spring 2007Lecture 25 - Subsystem Design7 Row/Column Memory Structure

8. ECE 425 Spring 2007Lecture 25 - Subsystem Design8 Hierarchical Memory Structure

9. ECE 425 Spring 2007Lecture 25 - Subsystem Design9 Memory Timing

10. ECE 425 Spring 2007Lecture 25 - Subsystem Design10 DRAM vs. SRAM Timing

11. ECE 425 Spring 2007Lecture 25 - Subsystem Design11 ROM Designs  Mask-Programmable - Set before fabrication  Field-Programmable - Fused connections  Electrically Programmable - Floating Gate Designs

12. ECE 425 Spring 2007Lecture 25 - Subsystem Design12 Mask-Programmable ROM - MOS NOR

13. ECE 425 Spring 2007Lecture 25 - Subsystem Design13 MOS NOR ROM - Contact-based Layout

14. ECE 425 Spring 2007Lecture 25 - Subsystem Design14 MOS NOR Layout - Implant-based Layout

15. ECE 425 Spring 2007Lecture 25 - Subsystem Design15 MOS NAND ROM

16. ECE 425 Spring 2007Lecture 25 - Subsystem Design16 MOS NAND ROM - Layout

17. ECE 425 Spring 2007Lecture 25 - Subsystem Design17 Nonvolatile ROM - Floating-Gate MOS Transistor (FAMOS)

18. ECE 425 Spring 2007Lecture 25 - Subsystem Design18 Programming a Floating-Gate Transistor (V T > V DD )

19. ECE 425 Spring 2007Lecture 25 - Subsystem Design19 Types of NV-RWM  EPROM (FAMOS)  Program using avalanch hot-electron injection  Erase using ultraviolet light  EEPROM (FLOTOX)  Program & erase using Fowler-Nordheim Tunneling  Advantage: elecrically eraseable  Flash EPROM  Program using avalanche hot-electron injection  Erase using Fowler-Nordheim tunneling

20. ECE 425 Spring 2007Lecture 25 - Subsystem Design20 FLOTOX EEPROM Transistors

21. ECE 425 Spring 2007Lecture 25 - Subsystem Design21 Flash EEPROM (ETOX) Transistor

22. ECE 425 Spring 2007Lecture 25 - Subsystem Design22 Characteristics of NV-RWM

23. ECE 425 Spring 2007Lecture 25 - Subsystem Design23 Volatile Read-Write Memory (RAM)  Static  Data stored as long as power on  Large (6 transistors/cell)  Fast  Differential  Dynamic  Periodic refresh required  Small (1-3 transistors/cell)  Slower  Single-Ended

24. ECE 425 Spring 2007Lecture 25 - Subsystem Design24 6-Transistor CMOS SRAM

25. ECE 425 Spring 2007Lecture 25 - Subsystem Design25 Layout - 6-Transistor CMOS SRAM

26. ECE 425 Spring 2007Lecture 25 - Subsystem Design26 3-Transistor Dynamic RAM

27. ECE 425 Spring 2007Lecture 25 - Subsystem Design27 Layout - 3T Dynamic RAM

28. ECE 425 Spring 2007Lecture 25 - Subsystem Design28 1 Transistor Dynamic RAM

29. ECE 425 Spring 2007Lecture 25 - Subsystem Design29 1 Transistor Dynamic RAM

30. ECE 425 Spring 2007Lecture 25 - Subsystem Design30 Advanced 1T Dynamic RAM Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate Trench Cell Stacked-capacitor Cell Capacitor dielectric layer Cell plate Word line Insulating Layer IsolationTransfer gate Storage electrode

31. ECE 425 Spring 2007Lecture 25 - Subsystem Design31 Subsystem Design  General TechniquesGoals  Pipelining  Datapath Design  Common Subsystems  Shifters  Adders  ALUs  Multipliers  Memories  Structured Logic 

32. ECE 425 Spring 2007Lecture 25 - Subsystem Design32 Programmable Logic Array (PLA)  Structured Two-Level Logic AND/OR  Similar to ROM, but with programmable AND array  Can be smaller than ROM for arbitrary logic functions  Once popular; importance now reduced Low performance Better software techniques (multi-level logic synthesis)  But, some ideas never die…  Basic forms  NOR-NOR (product of sums)  NAND-NAM (sum of products)

33. ECE 425 Spring 2007Lecture 25 - Subsystem Design33 Programmable Logic Array

34. ECE 425 Spring 2007Lecture 25 - Subsystem Design34 Pseudo-Static PLA

35. ECE 425 Spring 2007Lecture 25 - Subsystem Design35 Dynamic PLA

36. ECE 425 Spring 2007Lecture 25 - Subsystem Design36 Clock Signal Generation for self-timed dynamic PLA

37. ECE 425 Spring 2007Lecture 25 - Subsystem Design37 PLA Layout

38. ECE 425 Spring 2007Lecture 25 - Subsystem Design38 That’s all, folks!