1. Metal-Oxide-Semiconductor Field-Effect Transistor Digital Logic Technology
CMOS Fabrication
MOS Device Structure and Operation
NMOS Circuits
CMOS Circuits
The Future of CMOS Technology
BiCMOS Circuits
MOSFET – metal oxide semiconductor field effect transistor
ECE M. A. Jupina, VU, 2014

2. Some Key Lecture Objectives
A basic understanding of the layout and structure of MOS devices and circuits
A basic understanding of the electrical operation of MOSFETs
How logic functions can be synthesized in CMOS and why CMOS is the dominate digital technology today
A more fundamental understanding of power dissipation and propagation delay in CMOS technologies
The future of CMOS technology (FinFETs and TFETs)
When should BiCMOS technology be used and why
Reference:
Fundamentals of Digital Logic, Chapter 3 and references at
course website.
ECE M. A. Jupina, VU, 2014

3. CMOS Fabrication Processes
IC built on silicon substrate:
some structures diffused into substrate;
other structures built on top of substrate.
Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped)
Wires made of polycrystalline silicon (poly), multiple layers of aluminum/copper (metal).
Silicon dioxide (SiO2) is an insulator.
N-type semiconductor has an excess number of negative charge carriers (electrons).
P-type semiconductor has an excess number of positive charge carriers (holes).
ECE M. A. Jupina, VU, 2014

4. Simple Cross Section of a MOS Integrated Circuit
SiO2
metal3
metal2
metal1
via
transistor
poly
substrate n+ n+ p
substrate
ECE M. A. Jupina, VU, 2014

5. Example: Cross Section of Intel 0.25 Micron Process
Color Picture of the Intel 0.25 Micron Process
Tungsten vias and 5 layers of aluminum interconnects are shown
ECE M. A. Jupina, VU, 2014

6. CMOS Fabrication Processing Steps
First place tubs or wells to provide properly-doped substrate for nmos and pmos transistors:
p-tub
n-tub
substrate
Many CMOS techologies do not use “twin” tubs. Sometimes the nfets are fabricated directly in the p-type substrate (thus, no p-tub).
ECE M. A. Jupina, VU, 2014

7. Processing Steps, Cont’d.
Pattern polysilicon before diffusion regions:
gate oxide
poly
poly
p-tub
n-tub
ECE M. A. Jupina, VU, 2014

8. Processing Steps, Cont’d
Add diffusions (self-aligned source and drain)
poly
poly
p-tub n+ n+
n-tub p+ p+
ECE M. A. Jupina, VU, 2014

9. Processing Steps, Cont’d
Start adding metal layers:
metal 1
metal 1
vias
poly
poly
p-tub n+ n+
n-tub p+ p+
ECE M. A. Jupina, VU, 2014

10. Processing Steps, Cont’d
Add other metal interconnect layers:
metal 2
metal 1
metal 1
vias
Today, CMOS IC’s have as many as 6 to 9 metal layers to provide interconnections for circuits on the chip
poly
poly
p-tub n+ n+
n-tub p+ p+
ECE M. A. Jupina, VU, 2014

11. MOS Transistor Layout NMOS FET: PMOS FET: L L w w
Top View of the FET layout
Red – poly gate
Green – n-type region
Brown – p-type region
ECE M. A. Jupina, VU, 2014

12. NMOS Transistor Structure
ECE M. A. Jupina, VU, 2014

13. Transistor Sizes (a) Small transistor (b) Larger transistor + W L 2 1
In Digital Technology, L remains fixed and W is only changed to size the transistor.
As W/L ratio increases, the drain current increases.
ECE M. A. Jupina, VU, 2014

14. NMOS Transistor When Turned OffV = V G
SiO 2 V = V S V D
++++++
++++
++++++
++++++
+++
++++++
++++++
++++++
++++++
++++++
++++++
++++++
Substrate (type p)
Negative charge carriers due to electrons and positive charge carriers due to holes.
VT is the turn-on or threshold voltage of the MOSFET.
Source (type n)
Drain (type n)
When V
< VT, the transistor is off GS
ECE M. A. Jupina, VU, 2014

15. NMOS Transistor When Turned OnV DD V = 5 V G
SiO 2 V = V S V D
++++++
++++
+++
++++++
++++++
++++++ ++
Channel (type n)
When V
> VT, the transistor is on GS
ECE M. A. Jupina, VU, 2014

16. NMOS Transistor as a Switch
in = "low"
in = "high"
(a) A simple switch controlled by the input
Gate
Source
Drain
Substrate (Body)
(b) NMOS transistor V G V V S D
(c) Simplified symbol for an NMOS transistor
ECE M. A. Jupina, VU, 2014

17. PMOS Transistor as a Switch
in = "high"
in = "low"
(a) A switch with the opposite behavior
Gate
Drain
Source V DD
Substrate (Body)
(b) PMOS transistor V G V V S D
(c) Simplified symbol for an PMOS transistor
ECE M. A. Jupina, VU, 2014

18. NMOS and PMOS Transistors in Logic CircuitsV D V
= 0 V V D D V G V
= 0 V S
Closed switch
Open switch
when V = V
when V
= 0 V G DD G
(a) NMOS transistor V = V V V S DD DD DD V G V V V = V D D D DD
Open switch
Closed switch
when V = V
when V
= 0 V G DD G
(b) PMOS transistor
ECE M. A. Jupina, VU, 2014

19. The Current-Voltage Relationship of a NMOS Transistor
I D
Linear or
Triode
Saturation
ID,SAT V
> V GS T
ID,SAT – max drain current for a VGS value.
VDS,SAT = VGS - VT V DS
ECE M. A. Jupina, VU, 2014

20. NMOS Drain Current Characteristics
linear region for VGS > VT and VDS < (VGS - VT)
saturation, VGS > VT and VDS > (VGS - VT ).
subthreshold VGS < VT, VDS  0.
Sub-Threshold (ID=0)
ECE M. A. Jupina, VU, 2014

21. Drain Current Equations
For VGS > VT,
Linear region (VDS < VGS - VT)
Saturation region (VDS >= VGS - VT)
For VGS < VT, ID = 0 (Sub-Threshold region)
k’ – process transconductance parameter (A/V2) – depends on the physical parameters of the device, such as the thickness of the SiO2 gate oxide and how fast electrons or holes can move in the channel region between the source and drain in response to an electric field (this property is known as a carrier’s mobility which is velocity per electric field).
ECE M. A. Jupina, VU, 2014

22. NMOS and PMOS I-V Characteristics
Drain current–voltage characteristics for enhancement transistors: (a) for n-channel VDS, VGS, VT and IDS are positive; (b) for p-channel all these quantities are negative.
NMOS:
linear region for VGS > VT and VDS < (VGS - VT)
saturation, VGS > VT and VDS > (VGS - VT ).
subthreshold VGS < VT, VDS  0.
PMOS:
VGS < VT , VDS >VGS -VT : Linear
VGS < VT , VDS <VGS -VT : Saturation
VGS > VT, VDS <= 0 : Subthreshold
ECE M. A. Jupina, VU, 2014

23. An Inverter (NOT gate) Circuit for NMOS TechnologyDD R R +
5 V - V V f f V V x x
(a) Circuit diagram
(b) Simplified circuit diagram x f x f
(c) Graphical symbols
ECE M. A. Jupina, VU, 2014

24. Voltage Levels in an NMOS InverterDD DD DD
Load Line Analysis R R V f I V = V V = V
stat f OL f OH
Istat V R R x DS DS
-1/R
VOL
VOH=VDD
(c) V
(a) NMOS NOT gate
(b) V
= VDD=5V
= 0 x x
When VGS=Vx = VDD = 5V, NMOS is in the linear mode of operation and VDS is quite small where VDS=Vf=VOL and the ½ (VDS)2 term drops out of the above equation for RDS
When VGS=Vx = 0V, NMOS is in the subthreshold mode of operation and VDS=Vf=VOH=VDD (RDS is infinite, Istat = 0)
Load Line Analysis can also be performed to determine the operating conditions of the NMOS Inverter Circuit. The “load line” has a slope of -1/R. ~
ECE M. A. Jupina, VU, 2014

25. NMOS Realization of a NAND GateV DD V f V x 1 x x f 1 2 1 V x 2 1 1 1 1 1 1
(a) Circuit
(b) Truth table
Both transistors have to be “on” in the “pull-down” network for the output to be a logic low. x x 1 1 f f x x 2 2
(c) Graphical symbols
ECE M. A. Jupina, VU, 2014

26. NMOS Realization of a NOR Gate
Only one of the transistors have to be “on” in the “pull-down” network for the output to be a logic low.
ECE M. A. Jupina, VU, 2014

27. Structure of an NMOS Circuit
ECE M. A. Jupina, VU, 2014

28. Open Collector Examples
Wire-Anding
High Current External Loads
Special TTL gates with “open collectors” allow the outputs to be tied together so that “wire-anding” can be achieved.
Also these gates can be used to drive high current external loads.
An external load tied “high” is connected to the collector node of the output BJT so as to complete the output circuit.
Example: is an open collector inverter.
Open Drain logic devices are also available in MOS technologies.
Open Drain logic devices are also available in MOS technologies.
ECE M. A. Jupina, VU, 2014

29. Static Complementary CMOS Circuits
high noise margins - full rail to rail swing (VOH and VOL are at VDD and GND, respectively)
low output impedance, high input impedance
no steady state path between VDD and GND (no static power consumption)
delay is a function of load capacitance and transistor resistance
comparable propagation delay times (under the appropriate transistor sizing conditions)
logic levels not dependent upon the relative device sizes; ratioless
Static Complementary CMOS circuits - most widely used logic style
rail-to-rail - Vdd to 0V giving good noise margins
power dissipation - no path between Vdd and Gnd in steady state (ignoring leakage current)
ratioless - logic levels are not dependent upon relative device sizes (as in NMOS), so transistors can be minimum size
single inverter can theoretically drive an infinite number of gates and still be functionally operational; fan-out increases propagation delay
steady state path to Vdd or Gnd - low output impedance, so less sensitive to noise
Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes
- simpler, faster gates
- increased sensitivity to noise
ECE M. A. Jupina, VU, 2014

30. Static Complementary Gate Structure+
VDD
pullup
network
out
out in in
pulldown
network
Drain
VSS
ECE M. A. Jupina, VU, 2014 7

31. Switch Models of CMOS Inverter
VDD
VDD Rp
Vout = 0
Vout = VDD Rn
Rn or Rp is the equivalent on-resistance of the nmos or pmos device
Vin = V DD
Vin = 0
ECE M. A. Jupina, VU, 2014

32. Dynamic Current Flow in CMOS CircuitsV DD V I x D I D V V f f V x
(a) Current flow when input V
(b) Current flow when input V x x
changes from 0 V to 5 V
changes from 5 V to 0 V
ECE M. A. Jupina, VU, 2014

33. CMOS Power Dissipation
OFF ON
IAVER
Current flows only during the switching of the gate.
As the logic devices are switched at higher and higher frequencies, an additional transient current ( i(t) ) exists to charge and discharged the load (CL) at the output. This transient current ( i(t) ) increases as the switching frequency increases since the impedance of the load is decreasing as frequency is increasing. These additional switching or transient current levels thereby increase the power supply current levels drawn by the chip.
IAVER – the total DC or average current
The overall or total average power supply current increases as the switching frequency increases.
Total Power Dissipated = Static Power (due to ILEAKAGE) + Dynamic Power (due to switching current).
ILEAKAGE is a very small current (1- 10 nA per transistor). Can be neglected for SSI to LSI chips. For VLSI chips, the total ILEAKAGE from the 100’s of millions of transistors on that chip can create DC or static power dissipation equal to ~10% of the total power dissipated by the chip.
ECE M. A. Jupina, VU, 2014

34. Ways to Reduce CMOS Power Dissipation
Lower VDD – Hardware steps down supply voltage when system’s activity decreases (DVS)
Reduce Capacitance in logic circuits (minimize the size of transistors)
Lower fCLK – Hardware steps down clock frequency when system’s activity decreases (DFS)
Use Gated-Clock Circuits to power-off logic circuits when not being used
Clock
Can insert clock gating at
multiple levels in clock tree
Can shut off entire subtree
if all gating conditions are
satisfied
DVS – dynamic (supply) voltage scaling
DFS – dynamic (clock) frequency scaling
Clock
Disable
Signal
Gated
clock
ECE M. A. Jupina, VU, 2014

35. CMOS Propagation Delay
OFF
tpHL
tpHL
tpLH ON
ID,AVG, is the average transient or switching current.
Delta V is the change in the output voltage of the circuit between t = 0 and tpHL.
Rn or Rp is the equivalent on-resistance of the nmos or pmos device
ECE M. A. Jupina, VU, 2014

36. Examples of MOSFET Electrical Parameters
1 mm
0.25 mm
VDD (V) 5
2.5
kn’(mA/V2)
120
115
VTn (V)
0.8
0.43
kp’(mA/V2) 40 30
VTp (V)
-0.9
-0.4
L – length of the gate
Note: k’n is at least 3 times k’p. For this reason, Wp = 3 Wn so that IDp = IDn in the CMOS circuit. Therefore, the current drive levels and propagation delays are the same when the output goes high-to-low or low-to-high.
ECE M. A. Jupina, VU, 2014

37. CMOS NAND A B M 1 M2 M3 M4 F on off 1 A B A • B A B A F B M2 M1 M3 M4on
off 1 A B M2 M1
A • B A M3 M4 B A F B
ECE M. A. Jupina, VU, 2014

38. CMOS NOR A B M 1 M2 M3 M4 F 1 A on off 1 B A + B A B A F B M1 M2 M3 M41 A M1 on
off 1 B M2
A + B M3 A B M4 A F B
ECE M. A. Jupina, VU, 2014

39. CMOS Realization of an AND Gate
F = A • B A B
ECE M. A. Jupina, VU, 2014

40. Static Complementary CMOS
Pull-up network (PUN) and pull-down network (PDN)
VDD
PMOS transistors only
pull-up: make a connection from VDD to F when F(In1,In2,…InN) = 1
In1
In2
PUN …
InN
F(In1,In2,…InN)
In1
NMOS transistors only
pull-down: make a connection from F to GND when F(In1,In2,…InN) = 0
In2
PDN …
InN
One and only one of the networks (PUN or PDN) is conducting in steady state (output node is always a low-impedance node in steady state)
PUN and PDN are dual logic networks
ECE M. A. Jupina, VU, 2014

41. Construction of PDN NMOS devices in series implement a NAND function
NMOS devices in parallel implement a NOR function A B
A • B A B
A + B
ECE M. A. Jupina, VU, 2014

42. Dual PUN and PDN A + B = A • B A • B = A + B
PUN and PDN are dual networks
DeMorgan’s theorems
a parallel connection of transistors in the PUN corresponds to a series connection of the PDN
Complementary gate is naturally inverting (NAND, NOR, AOI, OAI)
Number of transistors for an N-input logic gate is 2N
A + B = A • B
A • B = A + B
ECE M. A. Jupina, VU, 2014

43. Complex CMOS Gate OUT = (D+A•(B+C)) B C A D A D B C
Shown synthesis of pull up from pull down structure
Max of 3 transistors in series (in the PUN) D B C
ECE M. A. Jupina, VU, 2014

44. Examples 3.1 and 3.2 in Textbook
These examples are found on pages 91 – 92 in the textbook.
ECE M. A. Jupina, VU, 2014

45. Given the PUN of a CMOS Circuit, Sketch the PDN
Given the PUN of a CMOS Circuit, Sketch the PDN. What is Logic Expression for F? F V DD A B C D F D C B A
F = (A+B)•(C+D)
ECE M. A. Jupina, VU, 2014

46. A Transmission Gate s s f x f Hi-Z 1 x s (a) Circuit (b) Truth table s
Hi-Z 1 x s
(a) Circuit
(b) Truth table s =
Another very popular way of combining nmos and pmos transistors to implement logic functions. A very useful gate! Logic gate synthesis with transmission gates usually reduces the number of transistors required to implement a logic function. x
f = Hi-Z s x f s = 1 x
f = x s
(c) Equivalent circuit
(d) Graphical symbol
ECE M. A. Jupina, VU, 2014

47. Exclusive-OR Gate ExampleB f = A Å B 1 1 A 1 1 f = A Å B B 1 1
(a) Truth table
(b) Graphical symbol A B
A SOP (sum-of-products) implementation by static complementary CMOS requires 22 transistors (11 nmos and 11 pmos since each inverter requires 1 nmos and 1 pmos transistor and each AND or OR gate requires 3 nmos and 3 pmos transistors). f = A Å B
(c) Sum-of-products implementation
ECE M. A. Jupina, VU, 2014

48. Exclusive-OR (XOR) Gate Implementation with Transmission Gates1 A B F Å =
off on 1 on B
2 static complementary CMOS inverters – 4 transistors
2 transmission gates – 4 transistors
Total = 8 transistors versus 22 transistors for SOP implementation by static complementary CMOS
A=0, F=B
A=1, F=not(B)
off
ECE M. A. Jupina, VU, 2014

49. Tri-State Buffer using TGsx e f e
= 0 x f e
= 1 x f
(a) A tri-state buffer
(b) Equivalent circuit e x f e
The inverters are implemented using static complementary CMOS.
A total of 8 transistors are used.
Tri-state buffer circuits are used as the output stage of CMOS circuits connected to Data Buses (where multiple devices are connected to the same data line).
Hi-Z 1
Hi-Z x f 1 1 1 1
(c) Truth table
(d) Implementation
ECE M. A. Jupina, VU, 2014

50. A 2-to-1 Multiplexer using TGsf 2
S=0 selects the X1 input.
S=1 selects the X2 input.
6 transistors are used.
ECE M. A. Jupina, VU, 2014

51. What is the Logic Function of This Circuit?F A B A B F 1 1 1
off on 1
off
off
The power supply lines change voltages for the CMOS inverter shown above.
When the source of the pmos fet is tied to 0 V and the source of the nmos fet is tied to VDD, both devices are off since VGSn is less than or equal to 0V and VGSp is greater than or equal to 0V for all input voltages between 0 and VDD at input B. 1 =B
ECE M. A. Jupina, VU, 2014

52. Standard Cell Frame Layout of CMOS Circuits
An example of a standard cell frame approach used in creating a standard cell VLSI library.
PMOS devices are placed at the top. NMOS devices are placed at the bottom.
The height of the standard cell frame is fixed so that the power busses, interconnects, transistor regions, etc line-up. The width of the cell frame can be varied, or we can simply use a standard width (Width=Height/2) and add frames end-to-end to create a wider frame.
Lambda is defined as the minimum dimension in a technology. The height of the standard cell frame shown is 78 lambdas.
Typically, the length of a MOSFET gate is 2*Lambda.
Note the “L” in the above figure is an abbreviation for the word lambda.
NMOS Transistors
PMOS Transistors
ECE M. A. Jupina, VU, 2014

53. A Simplified Floor Plan of a Standard Cell Design
VDD
Standard
Cells
GND
BUS
Routing
Channels
for
Wires
Pads
ASIC (Application Specific Integrated Circuit) example
Consisting of two separate blocks and a common signal bus
Standard cell library establishes what logic functions are possible in the chip design
ECE M. A. Jupina, VU, 2014

54. Standard Cell Layout Methodologyf a b
Routing
channel
VDD x x x x x
“Stick Diagram” x x x x x x
Route VDD and GND (power rails) horizontally
Route signals in poly (red) perpendicular to VDD and GND (vertically) – poly can serve as input to both nfets and pfets
Place diffusions (source and drain regions) in horizontal strips
The P+ source and drain regions of the PMOS transistors are shown in brown. The N+ source and drain regions of the NMOS transistors are shown in green.
Interconnections between cells are done in “routing channels.”
In this simple 2 metal scheme, Metal 1 (blue) is used to interconnect the transistors and Metal 2 (dark blue) is used for “vertical” routing of wires used to interconnect the standard cell circuits
Vias (connections between layers) shown as “X”.
GND
Routing
channel a f b
ECE M. A. Jupina, VU, 2014

55. Standard Cell Layout Methodologyf a b
Routing
channel
VDD G G G x x x x x S D D S S D x x G G G x x x x S D S D S D
Placement of the transistors inside the physical layout are now shown. Compare to previous slide. Note how the physical source and drain regions are shared between transistors next to one another. The poly regions are replaced by black wires. The metal interconnects and vias are shown for reference (these could be replaced with black wires for the final depiction of the circuit schematic).
GND
Routing
channel a f b
ECE M. A. Jupina, VU, 2014

56. Final Circuit Schematic of the Standard Cell
f = a • b a b
Final circuit schematic of the And gate (compare to previous slide).
ECE M. A. Jupina, VU, 2014

57. Standard Cell Layout of a CMOS Circuit
Microwind CAD Generated Drawing
“Stick” Drawing in Power Point
The CAD layout of an AND gate on the left was generated using the compile function in the Microwind 2.6a software. Note: PMOS transistors are larger than the NMOS transistors (Wp = 3 Wn).
The PMOS transistors (P+ source and drain regions shown in brown) are placed in a n-well or n-tub region (shown in green). The NMOS transistors (N+ source and drain regions shown in green) are placed in a p-type substrate (no p-well or p-tub region) and therefore the p-type substrate is not shown in this depiction.
A similar layout of an AND gate is shown in the drawing on the right. This was drawn in Power Point. Sizing of the transistors is not done in this “stick diagram” representation.
ECE M. A. Jupina, VU, 2014

58. Nanoscale MOS Technology
ECE M. A. Jupina, VU, 2014

59. Power Supply, Threshold Voltage, & Oxide Thickness Scaling with Channel Length Reduction
ECE M. A. Jupina, VU, 2014

60. Trends in MOS Device Scaling
Gate delay (speed) shown as a function of channel lengths.
ECE M. A. Jupina, VU, 2014

61. Constant Electric Field Scaling Example
Full scaling case illustrated.
Alpha is the scaling factor here.
ECE M. A. Jupina, VU, 2014

62. The Future (L  10 nm)
To improve performance, silicon will be mixed with a semiconductor like germanium to produce a more spacious, strained crystalline structure that lets electric charge carriers move faster.
To reduce the leakage of current that drives up power consumption, gate oxides will be made of materials with more than eight times the dielectric constant (k) of today’s silicon dioxide.
For better control of the transistor’s on and off states, gates will be of metal, instead of polysilicon.
For better control and (again) to reduce power consumption, gates themselves will be doubled up so that two will do the job a single gate does now.
For example, one promising High K material is hafnium dioxide with a dielectric constant of 22.
The need to maintain strong coupling between the gate and the channel as transistor dimensions shrink is indirectly the motivation for yet another materials change: metal gates. Today’s transistors have polysilicon gates so highly doped as to be almost as conductive as metal. But when they are biased, a depletion region about half a nanometer thick forms at the surface of the gate in contact with the insulator, adding to the effective thickness
of the gate oxide and so reducing coupling. A metal has a lot of carriers, so the depletion region is almost nonexistent. So, all else being equal, a metal gate will control the channel more strongly than a polysilicon gate.
ECE M. A. Jupina, VU, 2014

63. Higher Mobilities in Strained Si
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64. MOSFETs vs. FinFETs
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65. The FinFET
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66. Multi-Gate FinFETs TriGate Double Gate/ FinFET -Gate QuadGate
ECE M. A. Jupina, VU, 2014

67. Multi-Gate FinFETs Double-gate/ FinFET TriGate -Gate QuadGate
ECE M. A. Jupina, VU, 2014

68. FinFET Advantages
Excellent control of short channel effects in the deep submicron regime exists and transistors are still scalable. Due to this reason, the small-length transistor can have a larger intrinsic gain (transconductance) compared to MOSFETs.
Much lower off-state current compared to MOSFETs.
22 nm Tri-Gate FinFETs have a 37% performance increase and a 50% power reduction compared to 22 nm planar MOSFET technology at low voltages (< 1 V).
Allows MOS technology to stay on track with Moore’s Law.
ECE M. A. Jupina, VU, 2014

69. Intel Device Technology
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70. Intel’s Ivy Bridge: 3D ICs with FinFETs and TSVs
ECE M. A. Jupina, VU, 2014

71. After FinFETs, What Is Next?
p-type TFET
Tunnel field-effect transistors as energy-efficient electronic switches, Adrian M. Ionescu & Heike Riel
Nature 479,329–337(17 November 2011)doi: /nature10679
a, Schematic cross-section of p-type TFET with applied source (VS), gate (VG) and drain (VD) voltages. b, Schematic energy band profile for the off state (dashed blue lines) and the on state (red lines) in a p-type TFET. In the off state, no empty states are available in the channel for tunnelling from the source, so the off current is very low. Decreasing VG moves the valence band energy (EV) of the channel above the conduction band energy (EC) of the source so that interband tunnelling can occur. This switches the device to the on state, in which electrons in the energy window, ΔΦ (green shading), can tunnel from the source conduction band into the channel valence band. Electrons in the tail of the Fermi distribution cannot tunnel because no empty states are available in the channel at their energy (dotted black line), so a slope of less than 60 mV decade−1 can be achieved. This is indicated in the schematic transfer characteristics shown in c. In contrast to a conventional MOSFET, a TFET has a slope that is not linear on a logarithmic scale, which can be explained by the complex dependency of the tunnel current on the transmission probability through the barrier, as well as on the number of available states determined by the source and channel Fermi functions. The BTBT can be approximated by the triangular potential barrier indicated in grey. Because the tunnel current depends on the transmission probability through the barrier, as well as on the number of available states determined by the source and channel Fermi functions, the resultant slope is not linear on a logarithmic scale, which it is for a conventional MOSFET. λ, screening tunnelling length. a.u., arbitrary units; EF, Fermi energy.
ECE M. A. Jupina, VU, 2014

72. A Comparison of ID Versus VG in Various Devices
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu
& Heike Riel
Nature 479,329–337(17 November 2011)doi: /nature10679
Qualitative comparison of three engineering solutions to improve the characteristics of the bulk silicon MOSFET switch (red): a multigate device (MuG, blue) for improved electrostatics; a high-mobility channel (purple) using group III–V and SiGe materials; and a TFET (green), which has a steep off–on transition and the lowest IOFF. At operation point A, because of its subthermal subthreshold swing, the TFET offers not only an improved ION/IOFF but also a superior performance and a power saving at the same performance as a MOSFET. At operation point B, corresponding to higher performance, the MOSFET switch becomes the better solution
ECE M. A. Jupina, VU, 2014

73. TFET Advantages
■ Extends silicon-based CMOS technology possibly below 10 nm by enabling a new generation of device topologies while allowing the use of current manufacturing processes.
■ Steep sub-threshold slopes (below 60mV/decade) are possible, and therefore, even less leakage current in the "off" state
ECE M. A. Jupina, VU, 2014

74. BiCMOS
BiCMOS stands for Bipolar Complementary Metal-Oxide Semiconductor. BJTs and MOSFETs are used to construct logic gates.
Additional fabrication steps are required (increased cost).
BiCMOS advantages: Better switching speed than CMOS and lower power consumption than BJT logic circuits. p p p p+ p+ p
Complementary MOS offers an inverter with near-perfect characteristics such as high, symmetrical noise margins, high input and low output impedance, high gain in the transition region, high packing density, and low power dissipation. Speed is the only restricting factor, especially when large capacitors must be driven. In contrast, a BJT (bipolar junction transistor) logic gate has a high current drive per unit area, high switching speed, and low I/O noise. For similar fan-outs and a comparable technology, the propagation delay is about two to five times smaller than for the CMOS gate. However, this is achieved at a price. The high power consumption makes very large scale integration difficult. The typical BJT gate also has inferior dc characteristics compared to the CMOS gate—lower input impedance and smaller noise margins.
In recent years, improved technology has made it possible to combine complimentary MOS transistors and bipolar devices in a single process at a reasonable cost. A single n-epitaxial layer is used to implement both the PMOS transistors and bipolar npn transistors. Its resistivity is chosen so that it can support both devices. An n+-buried layer is deposited below the epitaxial layer to reduce the collector resistance of the bipolar device. The p-buried layer improves the packing density, because the collector-collector spacing of the bipolar devices can be reduced. It comes at the expense of an increased collector-substrate capacitance.
This technology opens a wealth of new opportunities, because it is now possible to combine the high-density integration of MOS logic with the current-driving capabilities of bipolar transistors. p p
ECE M. A. Jupina, VU, 2014

75. NPN Bipolar Junction Transistor (BJT): Physical Layout, Circuit Symbol, & Simplified Model
E – Emitter, B – Base, C – Collector
Two types of BJTs – npn and pnp
NPN BJTs switch faster than PNP BJTs since electrons (negative charged carriers) can achieve higher velocities than holes (positive charge carriers) in semiconductor materials. Therefore, NPN BJTs are used in digital logic applications.
Since the base region of the BJT is so narrow, the BJT is more than just two back-to-back diodes. A current-controlled current source is added to the model so that the “transistor-action” can be described. In the forward-active mode of operation, the BJT acts as current amplifier where the base current (IB) is amplified by the forward current gain (F ) of the BJT such that the collector current IC = F IB and the emitter current IE = (F +1) IB.
ECE M. A. Jupina, VU, 2014

76. Charge Storage in the Base of a NPN
n(x) x
EMITTER BASE COLLECTOR
Saturation
n(x) is the distribution of electrons stored in the base region as a function of x
QB is the total charge stored in the base and is proportional to the area under the n(x) plot
For the cutoff mode, the BJT is off and very little charge exists in the base.
For the two “on-modes,” saturation (“fully-on”) and forward active (partially-on”) modes, electrons are injected from the emitter into the base. From the base, the electrons travel into the collector. In saturation, more charge (electrons) is stored in the base, and therefore, the capacitance (C=Q/V where Q is the charge, V is the voltage, and C is the capacitance) of the BJT is larger than in the forward-active mode of operation. If a device’s capacitance increases, then its switching time increases, and thereby the propagation delay time of the logic circuit containing this device would increase. Therefore, to reduce the propagation delay time of logic circuits with BJT devices, the “on mode” should be the forward-active mode whenever possible.
An important part of the propagation delay is due to the base-charge buildup and removal. A fast bipolar logic gate should avoid having its transistors going into saturation, since this is where the major base-charge buildup happens.
Forward Active
Cutoff
ECE M. A. Jupina, VU, 2014

77. Operation of a BiCMOS Inverter
When the input is high, the NMOS transistor M1 is on, causing Q1 to conduct, while M2 and Q2 are off. The result is a low output voltage. A low Vin , on the other hand, causes M2 and Q2 to turn on, while M1 and Q1 are in the off-state, resulting in a high output level. In steady-state operation, Q1 and Q2 are never on simultaneously, keeping the power consumption low.
The impedances Z1 and Z2 are necessary to remove the base charge of the bipolar transistors when they are being turned off. For instance, during a high-to-low transition on the input, M1 turns off first. To turn off Q1, its base charge has to be removed. This happens through Z1. Adding these resistors not only reduces the transition times, but also has a positive effect on the power consumption. There exists a short period during the transition when both Q1 and Q2 are on simultaneously, thus creating a temporary current path between VDD and GND. The resulting current spike can be large and has a detrimental effect on both the power consumption and the supply noise. Therefore, turning off the devices as fast as possible is of utmost importance.
ECE M. A. Jupina, VU, 2014

78. Propagation Delay ECE 3450 M. A. Jupina, VU, 2014
The propagation delay of the BiCMOS inverter consists of two components:
(1) turning the bipolar transistors on (off)
(2) (dis)charging the load capacitor
It is important to keep the bipolar transistors out of the saturation region (“fully-on” mode of operation). Building and removing the base charge of a saturated transistor requires a considerable amount of time and results in a slow gate. One of the attractive features of the BiCMOS inverter is that the structure prevents both Q1 and Q2 from going into saturation. They are either in forward-active (“partially-on”) mode or cutoff (off). For the high output level, Q2 remains in the forward-active mode when VOH is reached. The PMOS transistor M2 acts a resistor, ensuring that the collector voltage of Q2 is always higher than its base voltage. Similarly, at the low-output end, M1 acts as a resistor between the base and the collector of Q1 , preventing the device from ever saturating. The base charge is, therefore, kept to a minimum, and the devices are turned on and off quickly.
Consequently, it is reasonable to assume that for typical capacitive loads, the delay is dominated by the capacitor (dis)charge times. To analyze the transient behavior of the inverter, assume that the load capacitance CL is the dominating capacitance. Consider first the low-to-high transition. Q1 is switched off fast, as its base charge is removed through Z1 . The load capacitor CL is charged by the current multiplier M 2-Q 2 . The source current of M 2 is fed into the base of Q2 and multiplied with the F of Q 2 (assuming that Q 2 operates in the forward-active region). This produces a large charging current of (F + 1) (V DD – VBE(on) - Vout ) / Ron (with Ron the equivalent on-resistance of the PMOS transistor). During the high-to-low transition, Q2 is turned off through Z 2. Once again, the combination M 1-Q 1 acts as a F current multiplier. Assuming that the resistance of M2 in the forward-active mode equals Ron , the discharge current equals (F + 1) (Vout - VBE(on) ) / Ron (assuming that Ron << Z1 ).
The current multiplication factor (F) makes the BiCMOS gate more effective than the CMOS inverter for large capacitive loads.
ECE M. A. Jupina, VU, 2014

79. Propagation Delay of BiCMOS and CMOS Gates as a function of CLtp
CLOAD CX
CMOS
BiCMOS
The BiCMOS inverter exhibits a substantial speed advantage over CMOS gates when driving large capacitive loads. This results from the current-multiplying effect of the bipolar output transistors.
For very low values of CL , the CMOS gate is faster than its BiCMOS counterpart due to the lack of capacitive loading by BJTs (a CMOS gate doesn’t have any BJTs). In BiCMOS, the MOSFETs are driving the BJTs which in turn drive the capacitive load CL of the gate. If these BJTs are under-utilized (ie, not driving a size-able CL), then these BJTs just add capacitance to the driving gate and thereby slow-down the overall switching speed of the gate.
For larger values of CL , the bipolar output transistors easily provide the extra drive current, and the BiCMOS gate becomes superior.
Although the cross-over point Cx is technology-dependent, it typically ranges from CL » 50 to 250 fF. As a result, BiCMOS inverters are normally used as buffers to drive large capacitances. They are not very effective for the implementation of the internal gates of a logic structure (such as an ALU), where the associated load capacitances are small. One must also remember that the complexity of the BiCMOS gate incurs an important area overhead on the chip. Careful consideration must be used to determine when and where to use BiCMOS structures .
ECE M. A. Jupina, VU, 2014

80. Applications of BiCMOS Circuits
Data Bus
On-Chip Clock Distribution Network
Composed of BiCMOS Inverters
BiCMOS (Tri-State) buffers to drive
off-chip loads
Off-chip capacitive loads are typically pico-Farads (pF is F) or more.
High quality (low skew and jitter) clock signals must be distributed across a chip. Typically, there is a large number of synchronous circuits that must be driven by a single clock signal on a chip, so the total capacitive load of these circuits is quite large (nano-Farads (nF is 10-9 F) on today’s microprocessors).
ECE M. A. Jupina, VU, 2014