1. CURRENT MIRROR/SOURCE EMT451/4

2. DEFINITION Circuit that sources/sinks a constant current as biasing elements as load devices for amplifier stages

3. CURRENT MIRRORS Principle : if the G-S potentials of two identical MOS transistors are equal, the channel currents should be equal. Mathematical perspective:  I D = f(V GS )=I ref for a MOSFET -> hence V GS = f -1 (I D )=f -1 (I ref ) i.e. apply V GS, get I ref, or transistor biased at I ref produces V GS  If the same voltage is applied to G and S of a second MOSFET, then I D =I out =f(V GS )=f[f -1 (I ref )]=ff -1 I ref =I ref  Another way of saying it: if we have two MOS devices with equal V GS in saturation, then they will carry equal currents

4. BASIC CURRENT MIRROR V DD R M2M2 M1M1 IoIo I REF The most basic current mirror circuit consists of 2 matching MOSFET transistors connected back to back, such that both have the same Gate-to-Source voltage.

5. Given: (*) The two enhancement-type NMOS transistors have matching features, as follows: V TH,1 = V TH,2, k n,1 ’ = k n,2 ’, λ 1 = λ 2 =0 (*) “By structure” we have that V GS,1 = V GS,2 (*) Typically the supply V DD, resistor R and a desired reference current I REF are all given. (*) The ratio (W/L) 1 is not necessarily equal to the ratio (W/L) 2 (*) “By structure” we have that V GD,1 = 0, and because the transistor is an enhancement-type, this guarantees that transistor 1 is always in Saturation Mode BASIC CURRENT MIRROR (cont’d)

6. Need: Using the transistors geometries (W/L) 1 and (W/L) 2 as design parameters, we want to create a DC current I o, as long as transistor M 2 is in Saturation Mode V DD R M2M2 M1M1 IoIo I REF BASIC CURRENT MIRROR (cont’d)

7. V DD R M2M2 M1M1 IoIo I REF The Drain of transistor M 2 is connected to a load circuit, not necessarily a resistor. The load circuit typically involves one or more additional MOSFET transistors. Depending on the load, transistor M 2 may be in any of three modes: Saturation, Triode or Cutoff. Of course, only when it is in Saturation it will work as originally planned (a DC current source) BASIC CURRENT MIRROR (cont’d)

8. V DD R M2M2 M1M1 IoIo I REF The current I o always goes away from the load circuit and into M 2. Such a DC current source is said to be a sink. BASIC CURRENT MIRROR (cont’d)

9. Design of a Current Mirror DC Sink We shall look first at M 1 : So, indeed if I REF is specified and V DD and R are given, then by the right-hand term the needed voltage V GS,1 is specified. Then, using the middle term, need to solve for (W/L) 1. V DD R M2M2 M1M1 IoIo I REF

10. Example 1: Let V DD = 5V, V TH,1 = 1V, k n,1 ' = 20μA/V 2 and R = 1KΩ. What should be (W/L) 1 needed for creating I REF = 1mA? V DD R M2M2 M1M1 IoIo I REF

11. Neglect CLM  = 0 IOIO VOVO + - V DD R M2M2 M1M1 IOIO I REF I D1 I D2 VOVO + - Let us now focus our attention on the "mirror" transistor M 2 : We now divide the two equations and use all the given matching parameters of the two transistors.

12. Example 2 (Follow-up to Example 1) What should be (W/L) 2 if we want I o = 7mA? Solution By Example 1 we have that I REF = 1mA and (W/L) 1 = 11.11. Therefore: V DD R M2M2 M1M1 IoIo I REF

13. Question: What do we do if we want to create a source DC current source, rather than a sink ? [A "source" is when the current goes from the current source into the load circuit] Answer: If we build a current mirror current source using PMOS transistors (rather than NMOS) then the output DC current will be "sourced" and not "sunk".

14. Question: If we need to generate multiple different DC current sources and sinks, what is the total number of resistors needed for the design? Answer: Just one resistor for the entire circuit!

15. Current Steering The use of a negative DC supply –V SS does not change the fact that, by-structure, both transistors, in every mirror pair, have the same V GS voltage. M2M2 M1M1 M3M3 M4M4 M5M5 V DD R I2I2 I REF I3I3 I4I4 I5I5 -V SS

16. Recalculation of Reference Current M2M2 M1M1 M3M3 M4M4 M5M5 V DD R I2I2 I REF I3I3 I4I4 I5I5 -V SS

17. NMOS Current Mirror Sinks: M2M2 M1M1 M3M3 M4M4 M5M5 V DD R I2I2 I REF I3I3 I4I4 I5I5 -V SS

18. Current Steering Mechanism: The Drain current of the NMOS transistor M 3 comes from the Drain of the PMOS transistor M 4. I 4 = I 3 Can "steer" a current from NMOS current mirror to PMOS current mirror, or vice versa. M2M2 M1M1 M3M3 M4M4 M5M5 V DD R I2I2 I REF I3I3 I4I4 I5I5 -V SS

19. There is no need for the NMOS and PMOS to be matching: Only all the NMOS transistors must match among themselves, and the PMOS transistors must be mutually matching. Current Steering Mechanism: M2M2 M1M1 M3M3 M4M4 M5M5 V DD R I2I2 I REF I3I3 I4I4 I5I5 -V SS

20. PMOS Current Mirror For the PMOS transistors M 4 and M 5, the following parameters must match: V TH,4 = V TH,5, k p,4 ’ = k p,5 ’, λ 4 = λ 5 M2M2 M1M1 M3M3 M4M4 M5M5 V DD R I2I2 I REF I3I3 I4I4 I5I5 -V SS

21. We can now relate the sourced current I 5 to the reference current I REF :

22. 1)We need only one resistor R, no matter how large is the number of DC currents generated. 2) By using current steering we can create sourcing currents from sinking currents or vice versa. 3) The reference current can reside either in a NMOS current mirror or in a PMOS current mirror. Summary:

23. Given: V DD = 5V, V SS = 0 V TH,1 = V TH,2 = V TH,3 = 1V, k n,1 ' = k n,2 '=k n,3 '= 20μA/V 2 and R = 1KΩ. V TH,4 = V TH,5 = -1V, k p,4 ' = k p,5 '= 30μA/V 2 Need: A reference current of I REF = 1mA, one sink current of 7mA and one source current of 5mA. Question: Using the diagram scheme just discussed, what should be all (W/L) ratios of all five transistors? Example ( a follow-up to the previous example)

24. The beginning of the solution is identical to what has been done in the previous examples. Let's quote the results: (W/L) 1 = 11.11 and (W/L) 2 = 77.77mA. Current I 2 is then the desired sink current Solution: M2M2 M1M1 M3M3 M4M4 M5M5 V DD R I2I2 I REF I3I3 I4I4 I5I5 -V SS

25. Now: There are infinitely many choices for the geometric dimensions of transistors M 3, M 4 and M 5. For instance, we may take (W/L) 3 = 11.11, (W/L) 4 = 10 and (W/L) 5 = 50. Current I 5 is then the required source current.

26. The channel-length modulation effect may be responsible for errors in the operation of a Current Mirror Current Source. For instance, depending on the load of M 2 we may get V DS,2 ≠ V DS,1. As a result the value of I 2 will slightly vary, depending on the load. It means that the current source is not ideal - it has a finite output resistance, equal to r o of the respective output transistor.

27. MULTIPLE CURRENT MIRROR Since there is no gate current in a MOSFET, a number of MOSFETs can be connected to a single reference MOSFET M 1. Different output currents can be obtained by suitably adjusting the width-to-length ratios of MOSFETs (i.e. M 2 and M 3 ). In practice, the gate length, L is normally kept constant and the gate width, W of M 2, M 3, and M 4 gives the relationship of the output currents I 2, I 3, and I 4 to I R as I 2 = (W 2 /W 1 )I R, I 3 = (W 3 /W 1 )I R, and I 4 = (W 4 /W 1 )I R The small-signal output resistance of the current source is, R o = r ds1 = 1/ I D1

28. MULTIPLE CURRENT MIRROR

29. CASCODE CURRENT MIRROR

30. WILSON CURRENT MIRROR