1. Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2012 Power and Ground Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr12

2. References  Q. K. Zhu, Power Distribution Network Design for VLSI, Hoboken, New Jersey: Wiley, 2004.  M. Popovich, A. Mezhiba and E. G. Friedman, Power Distribution Networks with On-Chip Decoupling Capacitors, Springer, 2008.  C.-K. Koh, J. Jain and S. F. Cauley, “Synthesis of Clock and Power/Ground Network,” Chapter 13, L.-T. Wang, Y.-W. Chang and K.-T. Cheng (Editors), Electronic Design Automation, Morgan- Kaufmann, 2009. pp. 751-850.  J. Fu, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan, Z. Pan, “VLSI On-Chip Power/Ground Network Optimization Considering Decap Leakage Currents,” Proc. Asia and South Pacific Design Automation Conf., 2005, pp. 735-738.  Decoupling Capacitors, http://www.vlsichipdesign.com/index.php/Chip-Design- Articles/decoupling-capacitors.html http://www.vlsichipdesign.com/index.php/Chip-Design- Articles/decoupling-capacitors.html http://www.vlsichipdesign.com/index.php/Chip-Design- Articles/decoupling-capacitors.html Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)2

3. Supply Voltage Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)3 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.25 0.18 0.13 0.1 Minimum feature size (μm) Supply voltage (V)

4. Gate Oxide Thickness Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)4 60 50 40 30 20 10 0 0.25 0.18 0.13 0.1 Minimum feature size (μm) Gate oxide thickness (A) High gate leakage

5. Power Supply Noise  Transient behavior of supply voltage and ground level.  Caused by transient currents:  Power droop  Ground bounce Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)5

6. Power Supply Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)6 +–+– Gate 1 Gate 2 VDD Rg RCRC RCRC V(t)

7. Switching Transients  Only Gate 1 switches (turns on): V(t) = VDD – Rg VDD exp[– t/{C(R+Rg)}]/(R+Rg) Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)7 V(t) VDD 0time, t VDD Rg/(R+Rg)

8. Multiple Gates Switching Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)8 Gate output voltage VDD 0time, t many Number of gates switching 1 2 3

9. Decoupling Capacitor  A capacitor to isolate two electrical circuits.  Illustration: An approximate model: Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)9 +–+– VDD = 1 Rg Rd Cd IL VL(t) t i(t) a t=0

10. Approximate Load Current, IL 0,t < 0 at,t < tp IL= a(2tp – t),t < 2tp 0,t > 2tp Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)10

11. Transient Load Voltage VL(t) = 1 – a Rg [ t – Cd Rg (1 – e – t/T ) ], 0 < t < tp T=Cd (Rg + Rd) Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)11

12. Realizing Decoupling Capacitor Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)12 GND SB D VDD GND SB D VDD OR

13. Capacitance Cd=γ×WL×ε×ε 0 /Tox ≈0.26fF, for 70nm BSIM L=38nm,W=200nm γ=1.5462 ε=4 Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)13

14. Leakage Resistance Igate=α × e – βTox ×W where α and β are technology parameters. Rd=VL(t)/Igate Because V(t) is a function of time, Rd is difficult to estimate. The decoupling capacitance is simulated in spice. Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)14

15. Power-Ground Layout Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)15 Vss Vdd Vss Vdd Solder bump pads M5 M4 Via Vdd/Vss supply Vdd/Vss equalization

16. Power Grid Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)16 +–+–

17. Nodal Analysis Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)17 V1 V2 V3 V4 Ci Vi Bi Apply KCL to node i: 4 ∑ (Vk – Vi) gk – Ci ∂Vi/∂t = Bi k=1 g1 g2 g3 g4

18. Nodal Analysis Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)18 G V – C V’ = B WhereG is conductance matrix V is nodal voltage vector C is admittance matrix B is vector of currents V(t) is a function of time, V(0) = VDD B(t) is a function of time, B(0) ≈ 0 or leakage current

19. Wire Width Considerations  Increase wire width to reduce resistance:  Control voltage drop for given current  Reduce resistive loss  Reduce wire width to reduce wiring area.  Minimum width restricted to avoid metal migration (reliability consideration). Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)19

20. A Minimization Problem Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)20 Minimize total metal area: n A= ∑ w i s i =∑ | ρ C i s i 2 | / x ii=1 Where n=number of branches in power network w i =metal width of ith branch s i =length of ith branch ρ=metal resistivity C i =maximum current in ith branch x i =voltage drop in ith branch Subject to several conditions.

21. Condition 1: Voltage Drop Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)21 Voltage drop on path P k : ∑ x i ≤Δv k i ε P k Where Δv k =maximum allowable voltage drop on kth path

22. Condition 2: Minimum Width Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)22 Minimum width allowed by fabrication process: w i =ρ C i s i / x i ≥W Where w i =metal width of ith branch s i =length of ith branch ρ=metal resistivity C i =maximum current in ith branch x i =voltage drop in ith branch W=minimum line width

23. Condition 3: Metal Migration Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)23 Do not exceed maximum current to wire-width ratio: C i / w i = x i /(ρ s i )≤σ i Where w i =metal width of ith branch s i =length of ith branch ρ=metal resistivity C i =maximum current in ith branch x i =voltage drop in ith branch σ i =maximum allowable current density across ith branch

24. Decoupling Capacitance Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)24 +–+– VDD Rg Cd I(t)

25. Decoupling Capacitance  Initial charge on Cd, Q 0 = Cd VDD  I(t): current waveform at a node  T: duration of current  Total charge supplied to load: T Q = ∫ I(t) dt 0 Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)25

26. Decoupling Capacitance  Assume that charge is completely supplied by Cd.  Remaining charge on Cd = Cd VDD – Q  Voltage of supply node = VDD – Q/Cd  For a maximum supply noise ΔVDDmax, VDD – (VDD – Q/Cd) ≤ ΔVDDmax OrCd≥Q / ΔVDDmax Spring 2012, Apr 4...ELEC 7770: Advanced VLSI Design (Agrawal)26