264. http://www.ece.umn.edu/users/kia/Courses/EE5324 Kia Bazargan
EE 5324 – VLSI Design II
Part VI: Testing
Kia Bazargan
University of Minnesota
Spring 2006
EE VLSI Design II - © Kia Bazargan
VLSI Design II – © Kia Bazargan

265. EE 5324 - VLSI Design II - © Kia Bazargan
Why Testing?
If you don’t test it, it won’t work! (guaranteed) [WE992]
Intel’s Pentium division bug (’94-’95)
Intel’s top ten slogans for Pentium: [ Oxford]
It’s a FLAW, dammit, not a bug
Redefining the PC – and math
Nearly 300 correct opcodes
Why do you think it’s called “floating” point?
. . .
Taking more and more of design cycle time
Have to plan for testing when designing
Why do we have different clock speeds for the same processor (133MHz, 166MHz, etc.)?
Gary Yeap’s experience (poly mask)
Spring 2006
EE VLSI Design II - © Kia Bazargan
VLSI Design II – © Kia Bazargan

266. EE 5324 - VLSI Design II - © Kia Bazargan
Testing Categories
Functionality tests
Done at each level of hierarchy (software+model) “Is architectural description equivalent to high-level?” “Is gate-level description equivalent to architectural?”
Higher levels of abstraction  faster
Modular design facilitates faster validation
Use diagnostic reasoning to find the bug
Manufacturing tests
Performed on the final product (wafer or package)
Transistor-level simulation and testing
“Are there any disconnected wires?” “Any layer-to-layer shorts?” “Is the product tolerant to Vdd variations?”
Spring 2006
EE VLSI Design II - © Kia Bazargan

267. Manufacturing Test Goals
Make testing fast
Provide controllability and observability
Controllability: ability to set internal nodes to desired values
Observability: ability to read internal node values
Challenge:
Limited number of pins
Some states might be impossible to generate
Methods
Provide circuitry to enable test
Provide test patterns that guarantee “reasonable” coverage (remember Pentium?)
Spring 2006
EE VLSI Design II - © Kia Bazargan

268. VLSI vs. Software Testing
Similarities
Syntax: design rules, electrical rules
Semantics: equivalence of specifications (verification)
Testing: does actual output match expected output
Debugging: similar diagnostic reasoning
Differences
Not all copies of a chip are identical — defects in fabrication
Access to internal state in debuggers, breakpoints, traces
Long turnaround from fabrication increase dependence on simulation at higher levels
[©Hauck]
Spring 2006
EE VLSI Design II - © Kia Bazargan

269. Designing to Reduce Errors
Layout and electrical rules: don't take chances (tradeoff density/speed)
Structured design styles
reduce degrees of freedom and details to handle
Modular design
Facilitate design changes, faster simulation
Cell libraries: reuse of existing validated designs
Timing methodologies: uniform style throughout system
Rules of composition: eliminate errors due to component interconnections
[©Hauck]
Spring 2006
EE VLSI Design II - © Kia Bazargan

270. Simulation at All Levels
Application specific simulators (C)
High-level / register-transfer-level hardware description languages for architecture simulation (VHDL, Verilog)
Logic level for mapping to gates
Switch level to verify logic structure implementation
Timing and performance level simulation involving analog effects (IRSIM)
Circuit characterization including all analog effects (SPICE)
Process simulation to mimic manufacturing process
[©Hauck]
Spring 2006
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271. EE 5324 - VLSI Design II - © Kia Bazargan
Product Testing
Characterization:
Are process params actually within allowable ranges?
Performed by fabrication service
Acceptance:
Binary decision to keep or throw away
Does chip perform all its functions correctly?
Both by fabrication service (limited) or designer (more complete)
Grading:
Grouping of chips into bins corresponding to performance
Performed by designer
[©Hauck]
Spring 2006
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272. EE 5324 - VLSI Design II - © Kia Bazargan
Types of Circuits
Combinational
2N inputs required to exhaustively test
Sequential
2M+N inputs required to exhaustively test
If each test vector takes 1ms, for M=50 and N=25, need 1 billion years to test! [WE92]
Combinational
Logic N K
Combinational
Logic N K M M
Registers
[WE92]
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EE VLSI Design II - © Kia Bazargan

273. Testing Methods Stored response: Comparison: Algorithmic:
Pre-stored output vectors compared to result of input vector
May need large storage for complex designs
Comparison:
Chip under test compared to known working unit in parallel
Eliminates storage requirements; easy to modify test
Algorithmic:
Expected output vectors computed on the fly by simulator
Most flexible but also slowest
Test
input vectors
Device Under Test (DUT)
Output vectors
[©Hauck]
Spring 2006
EE VLSI Design II - © Kia Bazargan

274. Generating and Validating Test Vectors
Automatic test-pattern generation (ATPG)
For given fault, determine test (aka excitation) vector that will propagate error to observable output
Most available tools: combinational networks only
Fault simulation
Determine minimal test vectors that will sensitize circuit to the fault
Simulates correct network in parallel with faulty networks
Structure of logic may make some faults untestable
Both require adequate models of faults in CMOS integrated circuits
[©Hauck]
[©Prentice Hall]
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275. EE 5324 - VLSI Design II - © Kia Bazargan
Faults
Hypothesize possible faults for which to test (may be layout dependent):
Stuck-at-0 (SA0), stuck-at-1 (SA1)
Node tied to Vdd or GND
Bridging (shorting)
Two wires tied together on one or more layers
Stuck-open
Break in a wire disconnects two wires
Delay faults
Parameter variations slow down a gate
Path-delay faults
Cumulative delay faults along a path
Multi-fault
Test for combination of faults not one at a time
[©Hauck]
Spring 2006
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276. EE 5324 - VLSI Design II - © Kia Bazargan
Fault Models
Stuck-at covers most of the faults
Shown: short (a,g), open (b)
a, g : x1 sa1
b : x1 sa0 or
x2 sa0 Z a x1 g x3 b x2
[©Prentice Hall]
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277. EE 5324 - VLSI Design II - © Kia Bazargan
Fault Models (cont.)
Stuck-at does not cover all faults
Example: Sequential effect:
Needs two vectors to detect
Other options:
Use stuck-open or stuck-short models
Problem: too expensive!
x1 x2 Z
0 x 1
1 1 0
1 0 Zn-1 x2 x1 Z x1 x2
[©Prentice Hall]
Spring 2006
EE VLSI Design II - © Kia Bazargan

278. Test Vector Generation: First Shot
F in presence of different stuck-at faults
ABC F Fm0 Fn0 Fp0 Fq0 Fm1 Fn1 Fp1 Fq1
ABC m0,n0,p0 q0 m1 n1 p1,q1
000 1
010 1
100 1
110
111 1
fault table A B C'
F = AB + C' m n p q
[©Hauck]
Spring 2006
EE VLSI Design II - © Kia Bazargan

279. Test Vector Generation: Path Sensitization
Work forward and backward from node of interest to determine values of inputs to test for fault
At the site of the fault, assign a logical value complementary to the fault
Select a path from the circuit inputs through the site of the fault to an output, the path is sensitized if the inputs to the gates along the path are set so as to propagate the value at the fault site
Determine the primary inputs that will produce the required values at the gate inputs as determined above
[©Hauck]
Spring 2006
EE VLSI Design II - © Kia Bazargan

280. Path Sensitization Example
Trigger the fault
Make it propagate to output
sa0 1
Fault enabling 1
Out
Fault propagation
[©Prentice Hall]
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EE VLSI Design II - © Kia Bazargan

281. Problems in Combinational Logic Testing
Untestable faults
Redundant logic (reconvergent fanout) can make some faults untestable
Is it necessary? (carry-bypass)
Computationally expensive
To determine minimum number of tests
Are all paths important?
Some paths may be unsensitizable (false paths)
Input combination may never occur
Multiple faults
One fault may invalidate test for another
Too expensive to model multiple-faults
[©Hauck]
Spring 2006
EE VLSI Design II - © Kia Bazargan

282. Testing Sequential Logic
Input vector sequence to get circuit into correct state and then another sequence to get result to a primary output
Testing of concealed state-intensive designs is impossible in practice
Make some state bits controllable and observable requiring less depth in sequence of input vectors
Make all state bits controllable and observable reducing problem to one of combinational circuit testing
[©Hauck]
Spring 2006
EE VLSI Design II - © Kia Bazargan

283. Level Sensitive Scan Design (LSSD)
Known as scan-based test
Scan path (shift register) links all state elements in circuit
Observe and control all states
Requires 3 extra pins and a bit more logic in FFs
All tests become combinational
Very slow — shift in test vector and shift out output vector serially — partial scan paths only use necessary amount
Easy to extend to system level
[©Hauck]
Spring 2006
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284. EE 5324 - VLSI Design II - © Kia Bazargan
Scan Based Test
ScanIn
ScanOut
Out
Register
Register
Combinational
Logic A
Combinational
Logic B In
[©Prentice Hall]
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285. EE 5324 - VLSI Design II - © Kia Bazargan
Scan Path Register
OUT
PHI2
SCAN
PHI1
SCANIN
SCANOUT IN
LOAD
KEEP
[©Prentice Hall]
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EE VLSI Design II - © Kia Bazargan

286. Scan-Based Test Operation
In0
In1
In2
In3
test
test
test
test
test
test
test
test
Scan In
Scan
Out
Latch
Latch
Latch
Latch
Out0
Out1
Out2
Out3
Test f1 f2
N cycles scan in
1 cycle
evaluation
N cycles scan out
[©Prentice Hall]
Spring 2006
EE VLSI Design II - © Kia Bazargan

287. Scan-Based Testing on Pipelined Designs
Efficient: use the existing registers A B
SCANIN
REG[1]
REG[0]
REG[2]
REG[3] +
REG[4]
COMPIN
COMP
SCANOUT
REG[5]
OUT
[©Prentice Hall]
Spring 2006
EE VLSI Design II - © Kia Bazargan

288. Boundary Scan (JTAG) Normal connections Printed-circuit board Logic
Packaged IC
Normal connections
Scan-in si so
Scan-out
scan path
Bonding Pad
[©Prentice Hall]
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EE VLSI Design II - © Kia Bazargan

289. addressable storage elements
Random Access Scan
When FFs arranged in memory like structure (limited class of designs)
Use decode logic to select FF to observe/control
Does not require shifting of all state elements — leads to faster tests
inputs
combinational logic
outputs
addressable storage elements in
out
r/w
address
[©Hauck]
Spring 2006
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290. EE 5324 - VLSI Design II - © Kia Bazargan
Self Testing
Built-in self test (BIST)
Chip itself generates test vectors (internally)
Dedicated sub-circuit to generate pseudo-random test vectors
Use “linear feedback shift register (LFSR)” to generate test vectors
Use signature to check the integrity
Apply sequences of input vectors and combine the output into a signature
Shift in initial seed and shift out the signature
Spring 2006
EE VLSI Design II - © Kia Bazargan

291. Linear-Feedback Shift Register (LFSR)
1 0 0
0 1 0
1 0 1
1 1 0
1 1 1
0 1 1
0 0 1
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EE VLSI Design II - © Kia Bazargan

292. BIST: Signature Analysis
Compress the output vector
Time compression (count # of transitions)
OR: compute output parity vector
Example: time compression: In
Counter R
[©Prentice Hall]
Spring 2006
EE VLSI Design II - © Kia Bazargan

293. Built-in Logic Block Observation (BILBO)
Built-in Logic Block Observation (BILBO) D0 D1 D2 B0 B1
ScanOut
ScanIn R R R S0 S1 S2 B0 B1
Operation mode
Introduced in 1979
Same hardware used for:
Pattern generation
Signature Analysis
Normal registers
Scan registers
Input data (Di) is XORed with the value of LFSR, acting as a seed 1 1
Normal
Scan 1
Pattern generation or signature analysis 1
Reset
[©Prentice Hall]
Spring 2006
EE VLSI Design II - © Kia Bazargan
VLSI Design II – © Kia Bazargan

294. BILBO – Pattern Generation
BILBO – Pattern Generation D0 =1 D1 D2
B0=1
B1=0
ScanOut
ScanIn R R R S0 S1 S2
Pattern generation mode
Set Di=1  XORs become NOT gates and negate the NOR gates  normal LFSR
Signature analysis mode
Let Di’s pass through. The signature is not very straightforward, but traceable B0 B1
Operation mode 1
Pattern generation or signature analysis
Spring 2006
EE VLSI Design II - © Kia Bazargan
VLSI Design II – © Kia Bazargan

295. BILBO – Pattern Generation vs. Signature Anal
BILBO – Pattern Generation vs. Signature Anal
In addition to the BILBO circuit shown in two slides ago, you may need some extra logic (e.g., multiplexers) that send either Di’s or 1’s
Pattern generation
simple LFSR
Signature analysis
Complex
But we can simulate and predict the correct values
Spring 2006
EE VLSI Design II - © Kia Bazargan
VLSI Design II – © Kia Bazargan

296. EE 5324 - VLSI Design II - © Kia Bazargan
BILBO Application
Scan in
BILBO 1
Comb
Logic 1
BILBO 2
Logic 2
BILBO 3
Logic 3
BILBO 4
Logic 4
BILBO 5 in
out
Scan out
Operation:
Seed sent in using the scan chain
Even BILBOs operate in pattern gen mode, odd ones in signature analysis
After a complete cycle (or desired # of cycles), odd BILBO values read through scan out
The same process repeats, this time with even BILBOs in signature analysis, odd ones in pattern generation
Feedback between different combination logics also possible, but treated as new comb inputs
Spring 2006
EE VLSI Design II - © Kia Bazargan
VLSI Design II – © Kia Bazargan

297. Memory Self-Test FSM Data in Memory Under Test Signature Analysis
Data out
Address & R/W Ctrl
Patterns: Writing/Reading 0s, 1s,
Walking 0s, 1s
Galloping 0s, 1s
[©Prentice Hall]
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EE VLSI Design II - © Kia Bazargan

298. To Probe Further (Testing)
BIST
K. A. Ockunzzi and C. Papachristou, "Test Strategies for BIST at the Algorithmic and Register-Transfer Levels", Design Automation Conference, pp , 2001.
LFSR
W. G. Solomon, “Shift Register Sequences”, Aegean Park Press, 1982.
Spring 2006
EE VLSI Design II - © Kia Bazargan