1. Adapted from Digital Integrated Circuits, 2nd Ed. 1 IC Layout

2. Adapted from Digital Integrated Circuits, 2nd Ed.2 Contents Software overview Design Rules and Design rules check (DRC) Layers  N-well  Active  Metals  Poly Interconnects  R, L, C  Propagation speed of signals in lines

3. Adapted from Digital Integrated Circuits, 2nd Ed.3 Design Software L-Edit Circuit at the mask (layout) level S-Edit Circuit at the Schematics level LVS consistency mask = schematic ? Simulation: T-Spice or any Spice based engine

4. Adapted from Digital Integrated Circuits, 2nd Ed.4 Design Software L-Edit Circuit at the mask (layout) level S-Edit Circuit at the Schematics level LVS consistency mask = schematic ? Simulation: T-Spice or any Spice based engine 1 2 3 4 5

5. Adapted from Digital Integrated Circuits, 2nd Ed.5 Process Layers

6. Adapted from Digital Integrated Circuits, 2nd Ed.6 The N-Well Assuming a p-type wafer, n- channel transistors are fabricated directly in the wafer; p-channel are fabricated in an “n-well” Processes with n-well over p- substrates are called n-well processes Substrate is also known as bulk or body N-well forms a diode (normally reverse biased) with the substrate

7. Adapted from Digital Integrated Circuits, 2nd Ed.7 N-Well: Design rules Every layer has certain rules to satisfy in order to be safely built MOSIS webpage data for AMI 0.5 R(N_Well) = 810Ω/□ Exercise: Layout and extract a resistor (minimum width) of 8K

8. Adapted from Digital Integrated Circuits, 2nd Ed.8 N-well diode capacitance Capacitance per area × bottom area Capacitance per area × depth of well × perimeter When the diode is reverse-biased (typical situation) Two components: bottom capacitance and sidewall capacitance

9. Adapted from Digital Integrated Circuits, 2nd Ed.9 N-well diode capacitance From MOSIS data, we know: Our resistor has a bottom capacitance And no more data … Approximate worst case RC

10. Adapted from Digital Integrated Circuits, 2nd Ed.10 Active Layer

11. Adapted from Digital Integrated Circuits, 2nd Ed.11 Active Layer Active layers, both n+ and p+ are used to make the source and drain of MOSFET’s Active defines the oxide mask where doping will take place: Regions outside Active have FOX (LOCOS) N select and P select define the doping mask

12. Adapted from Digital Integrated Circuits, 2nd Ed.12 Act Design Rules

13. Adapted from Digital Integrated Circuits, 2nd Ed.13 N+ and P+ rules

14. Adapted from Digital Integrated Circuits, 2nd Ed.14 Act contact rules In this case, there is a special contact to join metal and active

15. Adapted from Digital Integrated Circuits, 2nd Ed.15 Poly

16. Adapted from Digital Integrated Circuits, 2nd Ed.16 Poly Layer Polysilicon is made up of small crystalline regions of silicon Poly is used for the gates of MOS transistors They can make resistors and local connections for transistors

17. Adapted from Digital Integrated Circuits, 2nd Ed.17 Poly rules

18. Adapted from Digital Integrated Circuits, 2nd Ed.18 Poly contact rules

19. Adapted from Digital Integrated Circuits, 2nd Ed.19 Metal Layers

20. Adapted from Digital Integrated Circuits, 2nd Ed.20 The Metal layers Metal layers are used to interconnect devices (transistors, resistors, inductors and capacitors) Vias are used to interconnect the different metal layers Example: AMI 0.5 (three metals)

21. Adapted from Digital Integrated Circuits, 2nd Ed.21 Metal Design rules Metals 1, 2 and 3 rules  Spacing rules  Overlap rules Vias 1 and 2 rules In general, higher metal layers require bigger dimensions and spacing

22. Adapted from Digital Integrated Circuits, 2nd Ed.22 Metal 1 Design Rules: Separation

23. Adapted from Digital Integrated Circuits, 2nd Ed.23 Metal 1 Design Rules: Cnt Overlap

24. Adapted from Digital Integrated Circuits, 2nd Ed.24 Metal 2 rules: Separation

25. Adapted from Digital Integrated Circuits, 2nd Ed.25 Metal 2 Design Rules: via1 Overlap

26. Adapted from Digital Integrated Circuits, 2nd Ed.26 Metal 3 rules: Separation

27. Adapted from Digital Integrated Circuits, 2nd Ed.27 Metal 3 Design Rules: via2 Overlap

28. Adapted from Digital Integrated Circuits, 2nd Ed.28 Via 1 rules

29. Adapted from Digital Integrated Circuits, 2nd Ed.29 Via 2 rules

30. Adapted from Digital Integrated Circuits, 2nd Ed.30 Interconnects

31. Adapted from Digital Integrated Circuits, 2nd Ed.31 The Wire schematics physical

32. Adapted from Digital Integrated Circuits, 2nd Ed.32 Interconnect Impact on Chip

33. Adapted from Digital Integrated Circuits, 2nd Ed.33 Wire Models All-inclusive model Capacitance-only

34. Adapted from Digital Integrated Circuits, 2nd Ed.34 Impact of Interconnect Parasitics Interconnect parasitics  reduce reliability  affect performance and power consumption Classes of parasitics  Capacitive  Resistive  Inductive

35. Adapted from Digital Integrated Circuits, 2nd Ed.35 Nature of Interconnect Global Interconnect S Local = S Technology S Global = S Die Source: Intel

36. Adapted from Digital Integrated Circuits, 2nd Ed.36 INTERCONNECT: Capacitance

37. Adapted from Digital Integrated Circuits, 2nd Ed.37 Capacitance of Wire Interconnect

38. Adapted from Digital Integrated Circuits, 2nd Ed.38 Capacitance: The Parallel Plate Model

39. Adapted from Digital Integrated Circuits, 2nd Ed.39 Permittivity

40. Adapted from Digital Integrated Circuits, 2nd Ed.40 Fringing Capacitance

41. Adapted from Digital Integrated Circuits, 2nd Ed.41 Fringing versus Parallel Plate

42. Adapted from Digital Integrated Circuits, 2nd Ed.42 Interwire Capacitance

43. Adapted from Digital Integrated Circuits, 2nd Ed.43 Impact of Interwire Capacitance

44. Adapted from Digital Integrated Circuits, 2nd Ed.44 Wiring Capacitances (0.25 mm CMOS)

45. Adapted from Digital Integrated Circuits, 2nd Ed.45 AMI 0.5µm process capacitances Area capacitance (all values in aF/  m 2 ) Fringe capacitances (all values in aF/  m) M1M2M3 substrate321610 M13113 M231 M1M2M3 substrate765939 M15133 M252

46. Adapted from Digital Integrated Circuits, 2nd Ed.46 INTERCONNECT: Resistance

47. Adapted from Digital Integrated Circuits, 2nd Ed.47 Wire Resistance

48. Adapted from Digital Integrated Circuits, 2nd Ed.48 Interconnect Resistance

49. Adapted from Digital Integrated Circuits, 2nd Ed.49 Dealing with Resistance Selective Technology Scaling Use Better Interconnect Materials  reduce average wire-length  e.g. copper, silicides More Interconnect Layers  reduce average wire-length

50. Adapted from Digital Integrated Circuits, 2nd Ed.50 Polycide Gate MOSFET n + n + SiO 2 PolySilicon Silicide p Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 8-10 times better than Poly

51. Adapted from Digital Integrated Circuits, 2nd Ed.51 Sheet Resistance

52. Adapted from Digital Integrated Circuits, 2nd Ed.52 Modern Interconnect

53. Adapted from Digital Integrated Circuits, 2nd Ed.53 Example: Intel 0.25 micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric

54. Adapted from Digital Integrated Circuits, 2nd Ed.54 Resistance in AMI 0.5µm process Resistance A line of minimum width and 1mm long (1100 and 666 □ long, resp.) M1M2M3 Rs0.09Ω/□ 0.05 Ω/□ M1M2M3 Rs100 Ω 33 Ω

55. Adapted from Digital Integrated Circuits, 2nd Ed.55 Vias parasitics Vias exhibit a contact resistance given by the process They also have a current limitation given by the electromigration phenomenom. Typically, 0.5mA/cnt P+N+PolyM1M2M3 Contact R [Ω] 12657.516□0.820.79

56. Adapted from Digital Integrated Circuits, 2nd Ed.56 Metal Current Capacity Due to Electromigration, wire can be damagedElectromigration For Aluminum, the maximum current density (rule of thumb) is:

57. Adapted from Digital Integrated Circuits, 2nd Ed.57 INTERCONNECT: Inductance

58. Adapted from Digital Integrated Circuits, 2nd Ed.58 Metal Parasitics: L A metal line exhibits an inductance that can be estimated as: Assumption: w > h L is proportional to w and inversely prop. to h

59. Adapted from Digital Integrated Circuits, 2nd Ed.59 Metal Parasitics: L Ground bounce: The dI/dt along power lines actually produce a voltage drop due to the inductance Increase the width of the conductors supplying current Increase the capacitance of the conductors supplying current

60. Adapted from Digital Integrated Circuits, 2nd Ed.60 InterconnectModeling

61. Adapted from Digital Integrated Circuits, 2nd Ed.61 The Lumped Model

62. Adapted from Digital Integrated Circuits, 2nd Ed.62 The Lumped RC-Model: Elmore Delay

63. Adapted from Digital Integrated Circuits, 2nd Ed.63 The Ellmore Delay: RC Chain

64. Adapted from Digital Integrated Circuits, 2nd Ed.64 Wire Model Assume: Wire modeled by N equal-length segments For large values of N:

65. Adapted from Digital Integrated Circuits, 2nd Ed.65 The Distributed RC-line

66. Adapted from Digital Integrated Circuits, 2nd Ed.66 Step-response of RC wire as a function of time and space

67. Adapted from Digital Integrated Circuits, 2nd Ed.67 RC-Models

68. Adapted from Digital Integrated Circuits, 2nd Ed.68 Driving an RC-line

69. Adapted from Digital Integrated Circuits, 2nd Ed.69 Design Rules of Thumb rc delays should only be considered when t pRC >> t pgate of the driving gate Lcrit >>  t pgate /0.38rc rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line t rise < RC  when not met, the change in the signal is slower than the propagation delay of the wire © MJIrwin, PSU, 2000

70. Adapted from Digital Integrated Circuits, 2nd Ed.70 Appendix

71. Adapted from Digital Integrated Circuits, 2nd Ed.71 AMI 0.5 typical parameters (T36s)

72. Adapted from Digital Integrated Circuits, 2nd Ed.72 Appendix Poly resistor layout

73. Adapted from Digital Integrated Circuits, 2nd Ed.73 Poly: Resistor Design MOSIS webpage data for AMI 0.5 R(N_Well) = 22Ω/□ Exercise: Layout and extract a resistor (minimum width) of 1K. Try to make a square design Number of squares to achieve the desired resistance = 1000/22 □ = 45.5 Setting W = 2 then L = 91 Run DRC, extract and verify

74. Adapted from Digital Integrated Circuits, 2nd Ed.74 Folded Resistor Design: Folding the resistor leads to compact designs Squares and corners contribute partially to the material resistance

75. Adapted from Digital Integrated Circuits, 2nd Ed.75 Folded Resistor Design: Calculation for a square layout Assume Ns segments of width Ws, length Ls and spacing Wg The number of squares is: For a square design:

76. Adapted from Digital Integrated Circuits, 2nd Ed.76 Folded Resistor Design: For the 1K resistor,  N□ = 45.5  Ns=5.1  Ls=4.53