1. Nonlinear & Neural Networks LAB. CHAPTER 20 VHDL FOR DIGITAL SYSYEM DESIGN 20.1VHDL Code for a Serial Adder 20.2VHDL Code for a Binary Multiplier 20.3VHDL Code for a Binary Divider 20.4VHDL Code for a Dice Game Simulator 20.5Concluding Remarks

2. Nonlinear & Neural Networks LAB. Objectives 1. Given a block diagram and state graph for a digital system’s control unit. Write behavioral VHDL code for system. Use one clocked process 2. Compile and simulate VHDL code you wrote for step 1 3. Write synthesizable VHDL code for the system using control signals. Use two processes, one for combinational logic and one for updating registers 4. Compile, simulate, and synthesize the VHDL code for step.3 5. Write a VHDL test bench to test a VHDL module

3. Nonlinear & Neural Networks LAB. 20.1 VHDL Code for a Serial Adder Fig 20-1. VHDL Code for Figure 18-1

4. Nonlinear & Neural Networks LAB. Fig 20-1. (Continued) 20.1 VHDL Code for a Serial Adder

5. Nonlinear & Neural Networks LAB. 20.2 VHDL Code for a Binary Multiplier Fig 20-2. Behavioral VHDL Code for Multiplier of Figure 18-7

6. Nonlinear & Neural Networks LAB. Fig 20-2. (Continued) 20.2 VHDL Code for a Binary Multiplier

7. Nonlinear & Neural Networks LAB. Fig 20-2. (Continued) ‘ 0 ’ &ACC(7 downto 4) + Mcand 20.2 VHDL Code for a Binary Multiplier

8. Nonlinear & Neural Networks LAB. Fig 20-3. Command File and Simulation Results for (13 by 11) 20.2 VHDL Code for a Binary Multiplier

9. Nonlinear & Neural Networks LAB. Fig 20-4. Test Bench for Multiplier [loop-label:] for index in range loop sequential statements end loop [loop-label]; 20.2 VHDL Code for a Binary Multiplier

10. Nonlinear & Neural Networks LAB. Fig 20-5. Test Bench for Multiplier 20.2 VHDL Code for a Binary Multiplier

11. Nonlinear & Neural Networks LAB. Fig 20-5. (Continued) 20.2 VHDL Code for a Binary Multiplier

12. Nonlinear & Neural Networks LAB. Fig 20-6. Command File and Simulation of Multiplier 20.2 VHDL Code for a Binary Multiplier

13. Nonlinear & Neural Networks LAB. Fig 20-7. Two-Process VHDL Model for Multiplier 20.2 VHDL Code for a Binary Multiplier

14. Nonlinear & Neural Networks LAB. Fig 20-7. (Continued) 20.2 VHDL Code for a Binary Multiplier

15. Nonlinear & Neural Networks LAB. Fig 20-7. (Continued) 20.2 VHDL Code for a Binary Multiplier

16. Nonlinear & Neural Networks LAB. Fig 20-8. Block Diagram for 8X8 Binary Multiplier 20.2 VHDL Code for a Binary Multiplier

17. Nonlinear & Neural Networks LAB. Fig 20-9. VHDL Code for Multiplier with Shift Counter 20.2 VHDL Code for a Binary Multiplier

18. Nonlinear & Neural Networks LAB. Fig 20-9. (Continued) 20.2 VHDL Code for a Binary Multiplier

19. Nonlinear & Neural Networks LAB. Fig 20-9. (Continued) 20.2 VHDL Code for a Binary Multiplier

20. Nonlinear & Neural Networks LAB. Fig 20-10. Command File and Simulation of 8X8 Multiplier 20.2 VHDL Code for a Binary Multiplier

21. Nonlinear & Neural Networks LAB. 20.3 VHDL Code for a Binary Divider Fig 20-11. VHDL Code for Divider

22. Nonlinear & Neural Networks LAB. Fig 20-11. (Continued) 20.3 VHDL Code for a Binary Divider

23. Nonlinear & Neural Networks LAB. Fig 20-11. (Continued) 20.3 VHDL Code for a Binary Divider

24. Nonlinear & Neural Networks LAB. 20.4 VHDL Code for a Dice Game Simulator Fig 20-12. VHDL Code for Dice Game Controller

25. Nonlinear & Neural Networks LAB. Fig 20-12. (Continued) 20.4 VHDL Code for a Dice Game Simulator

26. Nonlinear & Neural Networks LAB. Fig 20-13. Counter Module for Dice Game 20.4 VHDL Code for a Dice Game Simulator

27. Nonlinear & Neural Networks LAB. Fig 20-14. Main Module for Dice Game 20.4 VHDL Code for a Dice Game Simulator

28. Nonlinear & Neural Networks LAB. 20.5 Concluding Remarks TABLE 20-1 Synthesis Results (Optimized for Area)