1. VLSI Design CMOS Transistor Theory

2. EE 447 VLSI Design 3: CMOS Transistor Theory2 Outline Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V Characteristics Gate and Diffusion Capacitance Pass Transistors RC Delay Models

3. EE 447 VLSI Design 3: CMOS Transistor Theory3 Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance I = C (  V/  t) ->  t = (C/I)  V Capacitance and current determine speed Also explore what a “degraded level” really means

4. EE 447 VLSI Design 3: CMOS Transistor Theory4 MOS Capacitor Gate and body form MOS capacitor Operating modes Accumulation Depletion Inversion Example with an NMOS capacitor

5. EE 447 VLSI Design 3: CMOS Transistor Theory5 Terminal Voltages Mode of operation depends on V g, V d, V s V gs = V g – V s V gd = V g – V d V ds = V d – V s = V gs - V gd Source and drain are symmetric diffusion terminals However, V ds  0 NMOS body is grounded. First assume source may be grounded or may be at a voltage above ground. Three regions of operation Cutoff Linear Saturation

6. EE 447 VLSI Design 3: CMOS Transistor Theory6 nMOS Cutoff Let us assume V s = V b No channel, if V gs = 0 I ds = 0

7. EE 447 VLSI Design 3: CMOS Transistor Theory7 NMOS Linear Channel forms if V gs > V t No Currernt if V ds = 0 Linear Region: If Vds > 0, Current flows from d to s ( e - from s to d) I ds increases linearly with V ds if V ds > V gs – V t. Similar to linear resistor

8. EE 447 VLSI Design 3: CMOS Transistor Theory8 NMOS Saturation Channel pinches off if V ds > V gs – V t. I ds “independent” of V ds, i.e., current saturates Similar to current source

9. EE 447 VLSI Design 3: CMOS Transistor Theory9 I-V Characteristics In Linear region, I ds depends on How much charge is in the channel How fast is the charge moving

10. EE 447 VLSI Design 3: CMOS Transistor Theory10 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate – oxide (dielectric) – channel Q channel =

11. EE 447 VLSI Design 3: CMOS Transistor Theory11 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate – oxide – channel Q channel = CV C =

12. EE 447 VLSI Design 3: CMOS Transistor Theory12 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversion Gate – oxide – channel Q channel = CV C = C g =  ox WL/t ox = C ox WL V = V gc – V t = (V gs – V ds /2) – V t C ox =  ox / t ox

13. EE 447 VLSI Design 3: CMOS Transistor Theory13 Carrier velocity Charge is carried by e- Carrier velocity v proportional to lateral E-field between source and drain v =  E  called mobility E = V ds /L Time for carrier to cross channel: t = L / v

14. EE 447 VLSI Design 3: CMOS Transistor Theory14 NMOS Linear I-V Now we know How much charge Q channel is in the channel How much time t each carrier takes to cross

15. EE 447 VLSI Design 3: CMOS Transistor Theory15 NMOS Saturation I-V If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs – V t Now drain voltage no longer increases current

16. EE 447 VLSI Design 3: CMOS Transistor Theory16 NMOS I-V Summary Shockley 1 st order transistor models (valid for Large channel devices only)

17. EE 447 VLSI Design 3: CMOS Transistor Theory17 Example For a 0.6  m process (MOSIS site)MOSIS site From AMI Semiconductor t ox = 100 Å  = 350 cm 2 /V*s V t = 0.7 V Plot I ds vs. V ds V gs = 0, 1, 2, 3, 4, 5 Use W/L = 4/2

18. EE 447 VLSI Design 3: CMOS Transistor Theory18 PMOS I-V All dopings and voltages are inverted for PMOS Mobility  p is determined by holes Typically 2-3x lower than that of electrons  n 120 cm 2 /V*s in AMI 0.6  m process Thus PMOS must be wider to provide same current In this class, assume  n /  p = 2

19. EE 447 VLSI Design 3: CMOS Transistor Theory19 Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important Creates channel charge necessary for operation Source and drain have capacitance to body Across reverse-biased diodes Called diffusion capacitance because it is associated with source/drain diffusion

20. EE 447 VLSI Design 3: CMOS Transistor Theory20 Gate Capacitance Approximate channel as connected to source C gs =  ox WL/t ox = C ox WL = C permicron W C permicron is typically about 2 fF/  m

21. EE 447 VLSI Design 3: CMOS Transistor Theory21 Diffusion Capacitance C sb, C db Undesirable, called parasitic capacitance Capacitance depends on area and perimeter Use small diffusion nodes Comparable to C g for contacted diff ½ C g for uncontacted Varies with process

22. EE 447 VLSI Design 3: CMOS Transistor Theory22 Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing V DD

23. EE 447 VLSI Design 3: CMOS Transistor Theory23 NMOS Pass Transistors We have assumed source is grounded What if source > 0? e.g. pass transistor passing V DD Let V g = V DD Now if V s > V DD -V t, V gs < V t Hence transistor would turn itself off NMOS pass transistors pull-up no higher than V DD -V tn Called a degraded “1” Approach degraded value slowly (low I ds ) PMOS pass transistors pull-down no lower than V tp Called a degraded “0” VsVs

24. EE 447 VLSI Design 3: CMOS Transistor Theory24 Pass Transistor Ckts

25. EE 447 VLSI Design 3: CMOS Transistor Theory25 Pass Transistor Ckts

26. EE 447 VLSI Design 3: CMOS Transistor Theory26 Effective Resistance Shockley models have limited value Not accurate enough for modern transistors Too complicated for much hand analysis Simplification: treat transistor as resistor Replace I ds (V ds, V gs ) with effective resistance R I ds = V ds /R R averaged across switching of digital gate Too inaccurate to predict current at any given time But good enough to predict RC delay

27. EE 447 VLSI Design 3: CMOS Transistor Theory27 RC Delay Model Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width k 

28. EE 447 VLSI Design 3: CMOS Transistor Theory28 RC Values Capacitance C = C g = C s = C d = 2 fF/  m of gate width Values similar across many processes Resistance R  6 K  *  m in 0.6um process Improves with shorter channel lengths Unit transistors May refer to minimum contacted device (4/2 ) Or maybe 1  m wide device Doesn’t matter as long as you are consistent

29. EE 447 VLSI Design 3: CMOS Transistor Theory29 Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter

30. EE 447 VLSI Design 3: CMOS Transistor Theory30 Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter

31. EE 447 VLSI Design 3: CMOS Transistor Theory31 Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter

32. EE 447 VLSI Design 3: CMOS Transistor Theory32 Inverter Delay Estimate Estimate the delay of a fanout-of-1 inverter d = 6RC