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COMP541 Datapath & Single-Cycle MIPS

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1 COMP541 Datapath & Single-Cycle MIPS
Montek Singh Mar 25, 2015

2 Topics Complete the datapath Add control to it
Create a full single-cycle MIPS! Reading Chapter 7 Review MIPS assembly language Chapter 6 of course textbook Or, Patterson Hennessy (inside front flap)

3 A MIPS CPU reset clk clk pc memwrite Instr Memory MIPS CPU Data Memory
dataaddr writedata instr readdata

4 Top-Level: MIPS CPU + memories
reset clk Top-level module MIPS CPU Instr Memory Data pc instr memwrite dataaddr readdata writedata clk reset We will add I/O devices (display, keyboard, etc.) later

5 One level down: Inside MIPS
Datapath: components that store or process data registers, ALU, multiplexors, sign-extension, etc. we will regard memories as outside the CPU, so not part of the core datapath Control: components that tell datapath what to do and when control logic (FSMs or combinational look-up tables) MIPS CPU Control ALUFN, regwrite, regdst… opcode, func, flagZ … MIPS Datapath Instr Memory Data pc instr memwrite dataadr readdata writedata clk reset clk

6 Review: MIPS instruction types
Three instruction formats: R-Type: register operands I-Type: immediate operand J-Type: for jumps

7 Review: Instruction Formats

8 R-Type instructions Register-type 3 register operands: Other fields:
rs, rt: source registers rd: destination register Other fields: op: the operation code or opcode (0 for R-type instructions) funct: the function together, op and funct tell the computer which operation to perform shamt: the shift amount for shift instructions, otherwise it is 0

9 R-Type Examples Note the order of registers in the assembly code:
add rd, rs, rt

10 I-Type instructions Immediate-type 3 operands: op: the opcode
rs, rt: register operands imm: 16-bit two’s complement immediate

11 I-Type Examples Note the differing order of registers in the assembly and machine codes: addi rt, rs, imm lw rt, imm(rs) sw rt, imm(rs)

12 J-Type instructions Jump-type 26-bit address operand (addr)
Used for jump instructions (j)

13 Summary: Instruction Formats

14 MIPS State Elements We will fill out the datapath and control logic for basic single cycle MIPS first the datapath then the control logic

15 We will not be implementing the textbook version of MIPS in our labs.
MIPS Design from Comp411 We will not be implementing the textbook version of MIPS in our labs. Instead, we will implement the MIPS design from Comp411, which has more features.

16 Design Approach “Incremental Featurism”
We will implement circuits for each type of instruction individually, and merge them (using MUXes, etc). Steps: 1. 3-Operand ALU instrs 2. ALU w/immediate instrs 2. Loads & Stores 3. Jumps & Branches 4. Exceptions (briefly) Our Bag of Components: Registers 1 Muxes ALU A B ALU & adders + Data Memory WD A RD R/W Register File (3-port) RA1 RA2 WA WE RD1 RD2 Instruction D Memories

17 Review: The MIPS ISA OP 6 5 16 26 The MIPS instruction set as seen from a Hardware Perspective 000000 rs rt rd func shamt R-type: ALU with Register operands Reg[rd]  Reg[rs] op Reg[rt] 001XXX rs rt immediate I-type: ALU with constant operand Reg[rt]  Reg[rs] op SEXT(immediate) Instruction classes distinguished by types: 3-operand ALU ALU w/immediate Loads/Stores Branches Jumps 10X011 rs rt immediate I-type: Load and Store Reg[rt]  Mem[Reg[rs] + SEXT(immediate)] Mem[Reg[rs] + SEXT(immediate)]  Reg[rt] 10X011 immediate rs rt I-type: Branch Instructions if (Reg[rs] == Reg[rt]) PC  PC *SEXT(immediate) if (Reg[rs] != Reg[rt]) PC  PC *SEXT(immediate) 00001X 26-bit constant J-type: jump PC  (PC & 0xf ) | 4*(immediate)

18 Fetching Sequential Instructions
32 + 4 32 P C Read Address Instruction Memory 32 register We will talk about branches and jumps later.

19 Instruction Fetch/Decode
Use a counter to FETCH the next instruction: PROGRAM COUNTER (PC) use PC as memory address add 4 to PC, load new value at end of cycle fetch instruction from memory use some instruction fields directly (register numbers, 16-bit constant) decode rest of the instruction use bits <31:26> and <5:0> to generate controls PC 00 A Instruction 32 Memory +4 D 32 32 INSTRUCTION WORD FIELDS OP[31:26], FUNC[5:0] Control Logic CONTROL SIGNALS

20 3-Operand ALU Data Path rs rt rd
000000 rs rt rd 100XXX 00000 R-type: ALU with Register operands Reg[rd]  Reg[rs] op Reg[rt] PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> RA1 Register RA2 Rd: <15:11> WA File WD RD1 RD2 WE WERF 32 32 Control Logic A B ALU ALUFN WERF! ALUFN WERF 32

21 Shift Instructions rs rt rd
000000 rs rt rd 000XXX shamt R-type: ALU with Register operands sll: Reg[rd]  Reg[rt] (shift) shamt sllv: Reg[rd]  Reg[rt] (shift) Reg[rs] PC 00 Instruction Memory A D +4 Rt: <20:16> Rs: <25:21> RA1 Register RA2 Rd: <15:11> WA File WD RD1 RD2 WE WERF shamt:<10:6> Control Logic 1 ASEL A B ALU ALUFN ASEL! ALUFN WERF ASEL 32

22 ALU with Immediate rs rt I-type: ALU with constant operand
001XXX rs rt immediate I-type: ALU with constant operand Reg[rt]  Reg[rs] op SEXT(immediate) PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> BSEL Rd:<15:11> Rt:<20:16> 1 RA1 Register RA2 WA WA File WD RD1 RD2 WE WERF ASEL 1 shamt:<10:6> imm: <15:0> SEXT SEXT 1 BSEL Control Logic How do you build SEXT? 1  pad with sign 0  pad with 0s SEXT A B ALU BSEL! BSEL ALUFN ALUFN WERF ASEL

23 Load Instruction rs rt 100011 I-type: Load
immediate I-type: Load Reg[rt]  Mem[Reg[rs] + SEXT(immediate)] PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> BSEL Rd:<15:11> Rt:<20:16> 1 RA1 Register RA2 WA WA File WD RD1 RD2 WE WERF ASEL 1 shamt:<10:6> Imm: <15:0> SEXT SEXT Control Logic 1 BSEL SEXT A B BSEL ALU WD R/W Wr ALUFN WDSEL ALUFN Data Memory Wr 32 Adr RD WERF ASEL 32 WDSEL

24 Store Instruction rs rt I-type: Store
10X011 immediate I-type: Store Mem[Reg[rs] + SEXT(immediate)]  Reg[rt] PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> BSEL Rd:<15:11> Rt:<20:16> 1 RA1 Register RA2 WA WA File WD RD1 RD2 WE WERF ASEL 1 SEXT BSEL shamt:<10:6> Imm: <15:0> Control Logic 32 No WERF! SEXT A B BSEL ALU Data Memory RD WD R/W Adr Wr ALUFN WDSEL ALUFN Wr WERF ASEL WDSEL

25 PC<31:28>:J<25:0>:00
JMP Instructions PC<31:28>:J<25:0>:00 00001X 26-bit constant J-type: j: PC  (PC & 0xf ) | 4*(immediate) jal: PC  (PC & 0xf ) | 4*(immediate); Reg[31]  PC + 4 PCSEL 1 2 3 PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> WASEL J:<25:0> Rd:<15:11> 1 2 Rt:<20:16> RA1 Register RA2 31 WA WA File WD RD1 RD2 WE WERF ASEL 1 SEXT BSEL shamt:<10:6> Imm: <15:0> Control Logic PCSEL WASEL SEXT A B BSEL ALU Data Memory RD WD R/W Adr Wr ALUFN WDSEL ALUFN Wr WERF ASEL PC+4 32 WDSEL

26 PC<31:28>:J<25:0>:00
BEQ/BNE Instructions PC<31:28>:J<25:0>:00 rs rt BT 10X011 immediate PCSEL 1 2 3 R-type: Branch Instructions if (Reg[rs] == Reg[rt]) PC  PC *SEXT(immediate) if (Reg[rs] != Reg[rt]) PC  PC *SEXT(immediate) PC 00 Instruction Memory A D That “x4” unit is trivial. I’ll just wire the input shifted over 2–bit positions. +4 Rs: <25:21> Rt: <20:16> WASEL Rd:<15:11> Rt:<20:16> 31 J:<25:0> 1 2 RA1 Register RA2 WA WA File WD RD1 RD2 WE WERF ASEL 1 SEXT BSEL shamt:<10:6> Imm: <15:0> Z x4 Why add, another adder? Couldn’t we reuse the one in the ALU? Nope, it needs to do a subtraction. Control Logic + PCSEL WASEL BT SEXT A B BSEL ALU Data Memory RD WD R/W Adr Wr ALUFN WDSEL ALUFN Wr Z WERF ASEL PC+4 32 WDSEL

27 Jump Indirect Instructions
PC<31:28>:J<25:0>:00 000000 rs rt rd 00100X 00000 JT BT PCSEL 1 2 3 R-type: Jump Indirect, Jump and Link Indirect jr: PC  Reg[rs] jalr: PC  Reg[rs], Reg[rd]  PC + 4 PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> WASEL Rd:<15:11> Rt:<20:16> 31 J:<25:0> 1 2 RA1 Register RA2 WA WA File WD RD1 RD2 WE WERF ASEL 1 SEXT BSEL shamt:<10:6> Imm: <15:0> JT Z BT + x4 Control Logic PCSEL WASEL SEXT A B BSEL ALU Data Memory RD WD R/W Adr Wr ALUFN WDSEL ALUFN Wr Z WERF ASEL PC+4 32 WDSEL

28 PC<31:28>:J<25:0>:00
Comparisons rs rt 001XXX immediate PC<31:28>:J<25:0>:00 JT BT I-type: set on less than & set on less than unsigned immediate slti: if (Reg[rs] < SEXT(imm)) Reg[rt]  1; else Reg[rt]  0 sltiu: if (Reg[rs] < SEXT(imm)) Reg[rt]  1; else Reg[rt]  0 PCSEL 1 2 3 PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> WASEL 31 1 2 J:<25:0> Rd:<15:11> RA1 Register Rt:<20:16> RA2 WA WA File WD RD1 RD2 WE WERF ASEL 1 SEXT BSEL shamt:<10:6> Imm: <15:0> JT Z BT + x4 Control Logic PCSEL WASEL SEXT A B BSEL ALU Data Memory RD WD R/W Adr Wr ALUFN WDSEL ALUFN Wr Z WERF ASEL PC+4 32 WDSEL

29 PC<31:28>:J<25:0>:00
More comparisons 000000 rs rt rd 10101X 00000 PC<31:28>:J<25:0>:00 JT BT R-type: set on less than & set on less than unsigned slt: if (Reg[rs] < Reg[rt]) Reg[rd]  1; else Reg[rd]  0 sltu: if (Reg[rs] < Reg[rt]) Reg[rd]  1; else Reg[rd]  0 PCSEL 1 2 3 PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> WASEL 31 1 2 J:<25:0> Rd:<15:11> Rt:<20:16> RA1 Register RA2 WA WA File WD RD1 RD2 WE WERF ASEL 1 SEXT BSEL shamt:<10:6> Imm: <15:0> JT Z BT + x4 Control Logic PCSEL WASEL SEXT A B BSEL ALU Data Memory RD WD R/W Adr Wr ALUFN WDSEL ALUFN Wr Z WERF ASEL PC+4 32 WDSEL

30 PC<31:28>:J<25:0>:00
LUI WA PC +4 Instruction Memory A D Register File RA1 RA2 RD1 RD2 ALU B WD WE ALUFN Control Logic Data Memory RD R/W Adr Wr WDSEL BSEL J:<25:0> PCSEL WERF 00 32 PC+4 Rt: <20:16> Imm: <15:0> ASEL SEXT I-type: Load upper immediate lui: Reg[rt]  Immediate << 16 Z BT WASEL PC<31:28>:J<25:0>:00 JT 001XXX immediate 00000 rt Rs: <25:21> 1 Rd:<15:11> Rt:<20:16> 2 shamt:<10:6> “16” 31 + x4 3

31 Reset, Interrupts, and Exceptions
Upon reset/reboot: Need to set PC to where boot code resides in memory Interrupts/Exceptions: any event that causes interruption in program flow FAULTS: e.g., nonexistent opcode, divide-by-zero TRAPS & system calls: e.g., read-a-character I/O events: e.g., key pressed How to handle? interrupt current running program invoke exception handler return to program to continue execution Registers $k0, $k1 ($26, $27) reserved for operating system (kernel), interrupt handlers any others used must be saved/restored

32 PC<31:28>:J<25:0>:00
Exceptions 0x 0x PC<31:28>:J<25:0>:00 Reset: PC  0x 0x JT BT Bad Opcode: Reg[27]  PC+4; PC  0x PCSEL 1 2 3 4 5 6 IRQ: Reg[27]  PC+4; PC  0x PC 00 Instruction Memory A D +4 Rs: <25:21> Rt: <20:16> WASEL Rd:<15:11> Rt:<20:16> 1 2 3 31 27 J:<25:0> RA1 Register RA2 WA WA File WD RD1 RD2 WE WERF Imm: <15:0> RESET SEXT JT SEXT IRQ Z BT + x4 ASEL 2 shamt:<10:6> “16” 1 Control Logic 1 BSEL PCSEL WASEL SEXT A B BSEL ALU Data Memory RD WD R/W Adr Wr ALUFN WDSEL ALUFN Wr Z WERF ASEL PC+4 32 WDSEL

33 Exceptions: Our Lab Version
We will not implement exceptions But: hardwire a “Reset” input which sets PC to 0, so it starts over WA PC +4 Instruction Memory A D Register File RA1 RA2 RD1 RD2 ALU B WD WE ALUFN Control Logic Data Memory RD R/W Adr Wr WDSEL BSEL J:<25:0> PCSEL WERF 00 32 PC+4 Rt: <20:16> Imm: <15:0> ASEL SEXT Z BT WASEL PC<31:28>:J<25:0>:00 JT Rs: <25:21> 1 2 3 RESET Reset: PC  0 shamt:<10:6> “16” Rd:<15:11> Rt:<20:16> 31 + x4

34 MIPS: Our Final Version
This is a complete 32-bit processor. Although designed in “one” class lecture, it executes the majority of the MIPS R2000 instruction set. WA PC +4 Instruction Memory A D Register File RA1 RA2 RD1 RD2 ALU B WD WE ALUFN Control Logic Data Memory RD R/W Adr WDSEL BSEL Wr J:<25:0> PCSEL WERF 00 32 (PC+4) Rt: <20:16> Imm: <15:0> ASEL SEXT Z BT WASEL PC<31:28>:J<25:0>:00 JT Rs: <25:21> 1 Rd:<15:11> Rt:<20:16> 2 shamt:<10:6> “16” 31 + <<2 3 RESET pc instr mem_addr mem_wr mem_readdata mem_writedata ReadData1 alu_result reg_writeaddr signImm aluA ReadData2 reg_writedata aluB pcPlus4 newPC Executes one instruction per clock

35 MIPS Control The control unit can be built as a large look-up table/ROM or, a case statement in Verilog! Instruction P C S E L S E X T WA S E L W D S E L ALUFN Sub Bool Shift Math W R W E R F A BS add x 1 xx sll andi lw sw beq …

36 Review: Our “full feature” ALU
Our ALU from Lab 3 (with support for comparisons) A B Result Bidirectional Shifter Boolean Add/Sub Sub Bool Shft Math Sub Bool Shft Math OP 0 XX A+B 1 XX A-B 1 X A LT B 1 X A LTU B X B<<A X B>>A X B>>>A X A & B X A | B X A ^ B X A | B 5-bit ALUFN <? Flags N,V,C Bool0 Z Flag

37 Summary We learned about a complete MIPS CPU
NOTE: Many details in textbook are different… … from what you will implement in the lab our lab MIPS has more features Next class: We will look at performance of single-cycle MIPS We will look at multi-cycle MIPS to improve performance Next lab: Implement single-cycle CPU!

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