1. ® Gate Array XC5200 Family A Low-cost Gate Array Alternative

2. ® www.xilinx.com XC5200 FPGA Family  Up to 23,000 gates  50-MHz system performance  Robust feature set  Unlimited reprogrammability  Pin-locking flexibility: VersaRingTM routing  5V devices

3. ® www.xilinx.com XC5200 Family Features  Gate array replacement success since 1995 —World’s fastest 5V FPGA volume ramp  A low cost FPGA/gate array alternative —Low cost, process-optimized architecture —5V, 0.5 micron process  High performance with robust feature set —Carry logic3-state buffers —Cascade chain4 global nets —JTAG logicSlew rate control

4. ® www.xilinx.com XC5200 Architecture Overview  Architecture highlights —VersaBlockTM logic module —VersaRing I/O interface —General Routing Matrix (GRM)

5. ® www.xilinx.com Abundant VersaBlock Routing  VersaBlock equals: —Configurable Logic Block (CLB) –4 identical Logic Cells –4 3-state buffers —Local Interconnect Matrix (LIM) –100% local connectivity –Up to 23 in, 8 out —Direct connects  Result: abundant local routing —Minimizes routing congestion —Granular and symmetrical

6. ® www.xilinx.com XC5200 Configurable Logic Block  Configurable Logic Block (CLB) —4 identical Logic Cells —20 inputs, 12 outputs —2 5-input functions  Logic Cell (LC0 - LC3) —Function generator, register, & control logic —Independently usable F & FD —Programmable flip-flop or latch —Fast carry logic or cascade chain —Independent feed- through

7. ® www.xilinx.com carry out XC5200 Carry Logic: 4-bit Adder

8. ® www.xilinx.com XC5200 Cascade Chain: 16-bit Decoder  Fast implementation of wide input functions  Adjacent CY_MUX connects to provide cascadable decode logic  Flexible LUT allows general decode, AND and OR cascade chains

9. ® www.xilinx.com XC5200 Family Efficient 5-Input Functions  Allows any combination of 2 separate 5-input functions in one CLB  LC0 and LC1 and/or LC2 and LC3 combined with F5_MUX  Unified library support: —F5MAP or F5_MUX  Efficient 4:1 muxes

10. ® www.xilinx.com Optimizing 5-Input Functions Both schematics will result in identical implementations Five input AND using F5_MUXFive input AND using F5MAP - or -

11. ® www.xilinx.com Implementing 4:1 MUX Using F5_MUX  Allows 4:1 muxes in 1/2 CLB

12. ® www.xilinx.com Single Length Lines Double Length Lines Direct Connects Longlines Local Interconnect Matrix Abundant Routing Resources  Six Levels of Hierarchy  General Routing Matrix —10 single-length lines —4 double-length lines —8 long lines per channel  VersaBlock —Local Interconnect Matrix —Direct connects to all neighbors —Logic cell feedthrough

13. ® www.xilinx.com XC5200 Global Line Network  4 global clock buffers  Direct access to all CLB clock pins (CK)  Access to non-clock pins via GRM  Buffers can be sourced by IOB or internal routing

14. ® www.xilinx.com XC5200 TBUF Connectivity  Four TBUFs/CLB  Any CLB output can drive any TBUF  “Weak-keeper” circuit maintains previous state  No pull-ups; use cascade chain for wired functions

15. ® www.xilinx.com VersaRingTM: High Utilization AND Pin Assignment Flexibility  Versatile interface between internal logic and I/O —I/O decoupled from core logic —Incremental edge routing  VersaRing resources —8 horizontal/vertical longlines —4 direct-connects in/out —4 double-length lines to GRM —10 single-length lines to GRM —8 single-length lines to adjacent VersaRing tile

16. ® www.xilinx.com XC5200 Input/Output Block  Selectable input, output or 3- state  Optional pull-up/pull-down  Dedicated boundary scan logic  8-mA output sink & source current  4 global nets  Programmable slew rate control  Programmable input delay line

17. ® www.xilinx.com XC5202XC5204XC5206XC5210XC5215 Max Logic Gates3,0006,00010,00016,00023,000 Typical Gate Range2-3K4-6K6-10K10-16K15-23K Logic Cells2564807841,2961,936 Flip-Flops2564807841,2961,936 Max I/O81124148196197 Performance-6/-5/-4/-3 -6/-5/-4/-3 -6/-5/-4/-3 -6/-5/-4/-3 -6/-5/-4/-3 Packages:VQ64 PC84PC84PC84PC84 PQ/VQ100PQ/VQ100PQ/VQ100 TQ144TQ144TQ144 PQ160PQ160PQ160PQ160 PQ208PQ208HQ208 PQ240HQ240 100% Footprint Compatibility in Common Packages XC5200 Family

18. ® www.xilinx.com XC5200 support to year 2005 and beyond XC5200 Success Since 1994 Revenue Units High Volume Design Wins Digital camera add-in card Cable modem Set-up box Video game CD player Graphics add-in card 10/100 Mbit Ethernet add-in cards High Volume Design Wins Digital camera add-in card Cable modem Set-up box Video game CD player Graphics add-in card 10/100 Mbit Ethernet add-in cards

19. ® www.xilinx.com Market Application Volume Consumer-VideoSet Top Box150,000 units Consumer-AudioHigh-end CD Player25,000 units Consumer-VideoVideo Game50,000 units Data ProcessingPC Add-in Card250,000 units Data ProcessingDisplay Monitor100,000 units CommunicationPCS Base Station25,000 units CommunicationModem Card100,000 units CommunicationVoice Mail50,000 units AutomotiveShock Absorber Control>100,000 units XC5200 Series Success

20. ® www.xilinx.com Xilinx XC5200 vs. Altera Flex 6K  XC5200 Advantages —Segmented interconnect —Lower power —Five XC5200 devices vs. three 6K devices —More features (flip-flop clock enables, cell feed- through, VersaRing, VersaBlock, etceteras.)  Altera Flex 6K is a poor copy of the innovative XC5200 architecture

21. ® www.xilinx.com FeatureXC5200Flex 6K Clock enableYesNo Direct feed-throughYesNo Independent logic & flip-flop outputs YesNo Clocks per flip-flop1:42:10 Logic Cells per block410 Logic Cell Comparison

22. ® www.xilinx.com XC5200 Benefit Summary  Process optimized architecture —Small die size —Unlimited reprogrammability —Up to 50-MHz performance  VersaRing I/O interface —Pin assignment flexibility —Logic change flexibility without requiring PCB relayout  100% footprint compatibility —Easy density migration within family

23. ® www.xilinx.com XC5200 Robust System Level Features  Fast carry logic —High-speed arithmetic functions  Dedicated JTAG logic —Eases system-level testability  3-state buffers —Efficient on-chip bussing  Cascade chain —Efficient wide-input functions