1. Requirements for the NSW VMM3 readout ASIC and the NSW Readout Controller ASIC NSW Readout Working Group NSW Electronics Design Reviews, February 2015

2. VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 2

3. VMM Present VMM2 has advanced analog circuitry, but only a simple readout architecture: a 4-deep buffer per channel – Read out, using a token passing mechanism, controlled by an external agent in response to an external trigger Require the usual pipelines to hold data until a trigger decision and then to push the data out via GBT standard E-links. Phase 2 compatible  both Level-0 and Level-1 pipelines Phase 1 Level-1:rate: 100 kHz;latency: 2.5  s Phase 2 Level-0:rate: 1 MHz;latency: 10  s (Phase 2 only) Phase 2 Level-1:rate: 400 kHz;latency: max 60  s (not fixed) Not practical to add this to an already very large, essentially analog chip Export all the data off chip requires noisy multi-Gb/s links or wide busses Compromise: split: L0 pipeline on VMM, L1 pipeline + fragment building + E-links on “ROC” VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 3

4. General requirements The number of bunch crossings read out for a trigger must be configurable from 1 to 8. Since several BCs may be read out per L0 trigger, a BC may belong to more than one trigger. (L0 allowed on consecutive BCs) E-link speeds: 80, 160 or 320Mb/s to match data rates of various FE boards Range is 40Mb/s to 440Mb/s per FE board.   Configurable E-link speed (allows optimizing GBT bank use)   Optionally more than one E-link output per ROC   Sub-ROCs for independent streams, or multi-lane E-links   Crossbar to route VMMs to SROCs (static, but configurable, routing), or round-robin (simpler, but can get out-of-order events) VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 4

5. Readout data flow paths from Front end to FELIX VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 5

6. VMM – ROC connections VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 6 ARTclk, ROclk = 160MHz

7. L0 pipeline in the VMM -- I 1 st of 2 options Hits are 37 bits Recall hits can belong to more than one trigger “Latency FIFO” actually a buffer as L0’s arrive Start of L0 BCID window is queued L0 selector discards hits older than window L0 selector copies hits within the window to output FIFO If moving hits to output cannot keep up, FIFOs can overflow flag bit available in hit word to indicate lost data. Note: in a 200ns (8BC) window there is at most one hit from a given channel VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 7

8. L0 pipeline in the VMM -- II 2 nd of 2 options Hits are 37 bits Recall hits can belong to more than one trigger “Latency FIFO” actually a buffer as L0’s arrive Start of L0 BCID window is broadcast to all L0 selectors Each L0 selector discards hits older than window Each L0 selector copies hits within the window to its private output FIFO Event building then takes place from the L0 filtered data in the FIFOs Looks more robust, but requires more resources Could queue L0’s as before with a handshake for the last L0 selector to finish Use simulation to decide which option and buffer sizes VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 8

9. Transfer from VMM to ROC The transfer is via two serial lines (even bits on one, odd bits on the other) running at 160 MHz with Double Data Rate (DDR) giving a total bandwidth of 640 Mb/s. Two lines are used to reduce the clock rate. – Max VMM output BW: 200MHz readout clock, two lines, DDR  800Mb/s but we use 160MHz to avoid changing the ePLL (This provides enough BW) 8b/10b net BW is 512Mb/s Use 8b/10b commas for sync and to delimit the (variable number of) hits in a L0 event packets – Hits rounded up to 40 bits, 50 bits after encoding – Event packet: hits from several VMMs and from several BCs, all within the BC window that includes the triggering BC. If no data for a L0, no packet is sent, only commas. VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 9

10. ROC internal routing VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 10 8 VMMs routed to up to 4 output E-links via a static, but configurable, routing to balance the load over the output E-links

11. ROC: Level-1 pipeline In parallel, each VMM capture deserializer and FIFO is receiving comma-delimited events consisting of hit words tagged by BCID For each L1A arriving via the TTC E-link, L1-ID ̶ L1-BCID pairs are stored in four FIFOs, one for each SROC. The BCID is the start of the BCID window Each SROC pulls its copy of the L1ID ̶ BCID pair and then pulls hits packets from its VMM FIFOs until a hit-BCID matches the L1-BCID. The hits in the packet are stored in the SROC derandomizing FIFO and finally serially transmitted on the SROC's E-link. – A header and a trailer (with checksum) are added to the event packet If there are no hits for a given Level-1 accept, multiple pairs of 8b/10b comma characters are sent i.e. not even a header. VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 11

12. TTC E-link VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 12 FELIX injects TTC data into an E-link Phase 2: TTC via FELIX formats to be decided by FELIX and TTC groups Possible for Phase 2: – L1A  L0A – B-chan must transmit BCID of L1A recall: L1-Accept will not have fixed latency could use bits[7..4] for a wider B-chan From 40MHz BC E-link clock, ePLL generate clocks for the 80, 160, 320Mb/s E-links and 160MHz design clock FELIX Phase 1 options with legacy TTC E-link widthbit 0bit 1bit 2bit 3bit 4bit 5bit 6bit 7 2 bitsA-chanB-chan 4 bits L1ABCRECRuser or B-chan 8 bits L1ABCRECRuser or B-chanuser example: test pulsereset

13. Configuration, Test pulse, reset The VMM and ROC will be configured via an SCA ASIC. The VMM configuration/monitor path must be operable independently of the acquisition state. The VMM must provide a buffer overflow counter (per channel or per VMM?) to be read by the SCA. Each VMM must have a its own configuration connection to the SCA. Each VMM must have a dedicated test pulse pin and a test pulse enable configuration bit. In response to the test pulse input, the VMM should generate the test pulse on the next BC clock. The ROC should generate test pulse for the VMM in response to a TTC test pulse bit. Resets: full reset (via pin and on power up); reset all but configuration registers VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 13

14. Configuration parameters ROC configuration parameters ROC ID BCoffset Size of trigger window (which neighboring BCs to read out on a Level-1 Accept) Select either the L1A or the L0A signal as the “L0A” signal sent to VMMs. For each VMM input: enable and mapping to SROC/E-link SROC output enables E-link speeds: 80, 160 or 320Mb/s Enable transmission of BUSY symbols New VMM configuration parameters Level-0 latency (BCs) Size of trigger window VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 14

15. Radiation tolerance Same TID as VMM: IBM 130nm OK Configuration registers and state machines must use TMR for SEU protection – Open issue: Hamming code or parity for FIFOs, or neither The VMM and ROC must provide an SEU flag or counter to be read by the SCA. ROC and VMM (and other NSW ASICs) must be tested in radiation to assess SEU rate and any increase of power consumption due to leakage current VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 15

16. Expected SEU rate VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 16 ChipBlock Number of bits Memory Type SEU Rate (SEU/s)SEU MTBF VMM3Latency FIFO (64*40 bits)2560SRAM3.08E-063,7 days VMM364 x Latency FIFO (64*40 bits)163840SRAM1.97E-041,4 hours ROCFront-End FIFO (1024x32 bits)30720SRAM3.70E-057.5 hours ROC8 x Front-End FIFO (1024x32 bits)245760SRAM2.96E-0456 min ROCSROC FIFO (512x32 bits)16384SRAM1.97E-0514 hours ROC4 x SROC FIFO (512x32 bits)65536SRAM7.89E-053.5 hours

17. Fabrication, packaging, testing IBM 130 nm CMOS technology sharing the same wafer with the VMM3 chip and the other companion ASICs. Expect silicon area of 20mm 2, 200 pins, pad limited Depending on ball pitch, the package size will be 12x12mm 2 to 17x17mm 2 We are worried about packaging, bad experiences by many – Plan to test with wire bonding die to PCB VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 17

18. Open issues 1.Is Hamming code or parity needed in the internal FIFOs for SEU immunity? 2.Do we really need two output lines per VMM? Can this be a configurable option to reduce lines on the FEB? 3.Will the VMM3 use I2C or SPI for configuration? (Note that both are single ended whereas all other VMM signals are differential.) 4.Can the SCA operate at 1.2V in order to be compatible with the VMM and ROC supplied with 1.2V? 5.What do we need in order to do the timing calibration/alignment? 6.Does the ROC require programmable delays or other means of phase alignment to capture the serial stream from the VMM? 7.Or is the fact that the VMM readout clock comes from the ROC enough to synchronize the capture, given that each bit is present for 3.1nsec? 8.More detailed simulation of the effect on MM strip multiplicity as a function of radius and  due to the magnetic field. VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 18

19. Responsibilities Specification and requirements L. Levinson, Weizmann Institute of Science S. Martoiu, IFIN-HH Bucharest V. Polychronakos, Brookhaven National Laboratory VMM3 ASIC design G. de Geronimo, Brookhaven National Laboratory A. Gupta, Brookhaven National Laboratory ROC ASIC design and VMM3 buffer M. Ivanovici, Transilvania Univ. of Brasov, logic design & verification S. Martoiu, IFIN-HH Bucharest, implementation & verification C. Radu, Transilvania Univ. of Brasov, logic design P. Stefan, Transilvania Univ. of Brasov, logic design T. Tulbure, Transilvania Univ. of Brasov, logic design, ASIC implementation & verification VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 19

20. Thank you VMM3-ROC requirementsNSW Electronics Design Reviews, February 2015 20