1. MIPS Overview (with comparisons to x86)
CS 3339
Lecture 3.1
Apan Qasem
Texas State University
Spring 2015

2. Announcements
Quiz 0 graded

3. History First specification in the early 80s
lead by John Hennessy
Developed by MIPS Technologies
One of the first examples of RISC architecture
Load/store architecture
Successful pipeline implementation
Spawned other RISC ISAs
SPARC
Alpha
In the 80s and 90s SGI’s servers implemented MIPS ISA
Today, MIPS mostly used in embedded processors
Routers
PS2

4. MIPS Processor

5. Processor on a Board

6. Multicore Processors

7. Parallel Multicore Processor Architecture

8. Resources Green insert in Text front cover Appendix B
Overview of ISA
Appendix B
Comprehensive syntax and semantics
MIPS virtual machine
hecate.cs.txstate.edu
Project idea:
Write a simulator for a MIPS-like architecture
Add a feature of your choice and evaluate

9. Review What features of MIPS should we be interested in?
Types of instructions
Addressing modes
Registers
Instruction length
Instruction encoding
Number of operands
Supported Data Types

10. A Bus-based Datapath for MIPSrs rt rd
ExtSel IR
Opcode
ldIR
Imm
Ext
enImm 2
zero? A B
OpSel
ldA
ldB
ALU
enALU
control 2
enMem MA
addr
data
ldMA
Memory
busy
MemWrt
RegWrt
enReg
addr
data rs rt rd
32(PC)
31(Link)
RegSel
32 GPRs
+ PC ...
32-bit Reg 3
Bus 32
Microinstruction: register to register transfer (17 control signals)
MA  PC means RegSel = PC; enReg=yes; ldMA= yes
B  Reg[rt] means
RegSel = rt; enReg=yes; ldB = yes
Slide courtesy : Asanovic
CS252 S05

11. Microprogramming add $1, $2, $3 ALU: A  Reg[rs] B  Reg[rt]
Reg[rd]  func(A,B)
do instruction fetch
Register
file
ALU
Microcode is another layer of abstraction used to implement higher level machine code in actual hardware

12. Arithmetic Instruction Variants
Four types of integer arithmetic instructions
Signed add
Immediate addi
Unsigned addu 
Unsigned Immediate addiu
Two types of floating-point instructions
Single precision add.s
Double precision add.d

13. Multiply and Divide Instructions
Signed and unsigned multiply, divide
mult, multu, div, divu
Move result from multiply, divide
mfhi, mflo
Move to HI or LO
mthi, mtlo
Register
File HI LO

14. Logical Instructions Usual set of logical operations available
OR, AND, XOR etc.
Also supports many variants of shift
shift left logical sll // shift left by a constant
shift right logical srl // shift right by a constant
shift right arithmetic sra // shift right and sign extend
shift left logical sllv // shift left by variable (amt. in reg)
shift right logical srlv // shift right by variable (amt. in reg)
shift right arithmetic srav // shift right by variable and sign extend

15. Data Transfer Instructions
Loads and Stores
byte, word and half word variants available
word is most commonly used
sb, sw, sh
Unsigned and signed variants of load
lbu, lb
Can do immediate loads (moves, really)
lui $3, 64

16. beq $1, $2, offset // jump to PC + offset, if $1 = $2
Branch Instructions
Conditional and Unconditional branches supported
Comparison and branch are fused into one instruction
beq $1, $2, offset // jump to PC + offset, if $1 = $2
Many different variants available
PC-relative and immediate
Comparison with zero
bgtz, bgez
Used for normalized loops, boolean flags
Non-fused branches available too

17. Registers in MIPS 32 GP Integer registers ($0 - $31)
32 bits for MIPS32, 64 bits for MIPS64
$0 always holds 0
$sp = $29 = stack pointer
$gp = $28 = global pointer
$ra = $31 = return address
32 FP registers ($f0 - $f31)
16 double-precision, uses adjacent 32-bit registers
PC separate from register file
x86 has 8 GP registers
+ SP, PC, GP etc

18. MIPS Register Usage $zero constant 0 n.a. $at 1 reserved for assembler
Name
Register Number
Usage
Preserve on call?
$zero
constant 0
n.a.
$at 1
reserved for assembler
$v0 - $v1
2-3
returned values no
$a0 - $a3
4-7
arguments
yes
$t0 - $t7
8-15
temporaries
$s0 - $s7
16-23
saved values
$t8 - $t9
24-25
$gp 28
global pointer
$sp 29
stack pointer
$fp 30
frame pointer
$ra 31
return address

19. Instruction Length and Encoding
Simple fixed instruction format
90 instructions
3 types of encoding
R, I and J
ISA has pseudo instructions that are synthesized into simple sequences
rotate left (rol) is implemented using a combination of shift and mask
Designed for fast hardware (pipelining) + optimizing compilers
R: rd  rs1 op rs2 Op
RS1
RS2 RD
func 6 5 11
I: ld/st: rd  rs1 op imm, branch Op
RS1 RD
const 6 5 16
J: j, jal Op
const 6 26
Fixed-Format (MIPS)
x86 supports variable length
1 to 15 byte instructions

20. Number of Operands
Arithmetic and logical instructions use three operands
add $1, $2, $3
Destination register separate from source
All operands must be in registers
Most x86 implementations allow only two operands
One of the sources has to serve as destination
x86 allows one operand to be in memory

21. Memory Addressing and Access
Addressing modes
Immediate : address stored in instruction
Register : address stored in register
Relative : address = register + offset
Addressable Unit and Alignment
byte, half-word, word, double word [instruction dependent]
Endianness
Big endian (can operate as little endian as well)

22. Instruction Encoding
Describe the encoding of a sub instruction in the y85 architecture where one of the operands is in memory
Number of instructions in ISA is 16
Instruction length is 32 bits
Number of GP registers is 16
Memory size is 2 GB