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Jpeg Hardware Compression Chaitanya Vardhana – S/W Anthony Louviere – H/W & H/W TB Reazul Hasan – H/W & Tools.

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Presentation on theme: "Jpeg Hardware Compression Chaitanya Vardhana – S/W Anthony Louviere – H/W & H/W TB Reazul Hasan – H/W & Tools."— Presentation transcript:

1 Jpeg Hardware Compression Chaitanya Vardhana – S/W Anthony Louviere – H/W & H/W TB Reazul Hasan – H/W & Tools

2 JPEG Compression and Code VHDL code from opencores including TB and image.bmp (352x288 = 304,182 bytes) Max size of bitmap: 352x288 13 block RAMs for code/tables 25 block RAMs for output (52k bytes) 3 quantization (compression) levels RGB to YCbCrDownsamplingBlock Splitting DCTEntropy EncodingQuantization Bitmap Image JPEG Compressed Image

3 Interface Design and Considerations Biggest Limitation: Block RAMs – 32 Biggest Limitation: Block RAMs – 32 Reduced input image to 176x144 (76086 bytes) and the output RAM to 20k (16 Block RAMs) Reduced input image to 176x144 (76086 bytes) and the output RAM to 20k (16 Block RAMs) Inputs sent to H/W 4k pixels at a time Inputs sent to H/W 4k pixels at a time Packed one pixel of R,G,B (8 bytes each) into one 32 bit word with $00 in MSB Packed one pixel of R,G,B (8 bytes each) into one 32 bit word with $00 in MSB Input RAM @ 0xD3000000; Output RAM @ 0xD30004000; #Columns @ 0xCC000000; #Lines @ 0xCC000004; CSR @0xCC000008 Input RAM @ 0xD3000000; Output RAM @ 0xD30004000; #Columns @ 0xCC000000; #Lines @ 0xCC000004; CSR @0xCC000008 CSR: Buffer empty bit; Compression Factor; Mono; Image done bit; Buffer depth counter CSR: Buffer empty bit; Compression Factor; Mono; Image done bit; Buffer depth counter Endian-ness : Bitmap is little endian Endian-ness : Bitmap is little endian

4 Bitmap in S/W First two bytes are Big Endian and in ASCII “B” “M”. Rest is Little Endian First two bytes are Big Endian and in ASCII “B” “M”. Rest is Little Endian Header (typically 54 bytes): File size, #columns, #lines Header (typically 54 bytes): File size, #columns, #lines Image is stored upside down and right to left (bottom right to top left) Image is stored upside down and right to left (bottom right to top left) File size = $012936 = 76086 bytes Header size = $36 = 54 bytes #columns = $00B0 = 176 #lines = $0090 = 144 First Pixel: R-$D0, G-$BD, B-$57 (actually bottom right corner)

5 Input and Output in S/W Grab file size, header size, #columns, #lines and pixel data. Grab file size, header size, #columns, #lines and pixel data. Set the columns, and lines registers and the compression and mono bits in CSR. Set the columns, and lines registers and the compression and mono bits in CSR. Send 4096 pixels, set buffer counter, clear buffer_empty bit and wait for buffer_empty to be set again. Send 4096 pixels, set buffer counter, clear buffer_empty bit and wait for buffer_empty to be set again. Keep track of how many bytes are left in the file. Keep track of how many bytes are left in the file. Same addresses reused for every set of 4096 data Same addresses reused for every set of 4096 data After last block of data is sent start polling image_end bit. After last block of data is sent start polling image_end bit. When image_end is set, read the output ram. Look for “FFD9” which signifies end of JPEG. When image_end is set, read the output ram. Look for “FFD9” which signifies end of JPEG. Write JPEG data to output file Write JPEG data to output file Input Snippet: do { while((!image_end) && (*csreg_ptr & 0x00000001)){ for(;j<4096;j++) { if(array_cnt < image_size) { - pack bits into array element - track count image_end = 0; } else image_end = 1; } - set array count - write array elements to H/W - clear buffer_emtpy if(image_end) break; } while(1)

6 Logic Design Write Control Registers Write Control Registers Number of Columns, Rows, Buffer Depth, Compression Factor Number of Columns, Rows, Buffer Depth, Compression Factor Software Transfers Bitmap Image to RGB Buffers Software Transfers Bitmap Image to RGB Buffers Software sets buffer_empty register bit to initiate compression Software sets buffer_empty register bit to initiate compression Handshaking between control logic and compressor Handshaking between control logic and compressor Asserts ProcessRGB when bitmap data available Asserts ProcessRGB when bitmap data available Compressor Responds with asserting ProcessingRGB Compressor Responds with asserting ProcessingRGB Transfer done when buffer_depth is reached Transfer done when buffer_depth is reached Software continues to refill RGB buffer until the whole image is sent Software continues to refill RGB buffer until the whole image is sent Compressor writes compressed data to image buffer. Image_done bit is set once the compressor is finished Compressor writes compressed data to image buffer. Image_done bit is set once the compressor is finished Software transfers image buffer data to jpeg file Software transfers image buffer data to jpeg file

7 JPEG Compressor Testbench Written in VHDL Written in VHDL Bus Transaction Model Bus Transaction Model Simulates ARM R/W Cycles Simulates ARM R/W Cycles Bitmap Read Function Bitmap Read Function Parses Uncompressed Bitmap file Parses Uncompressed Bitmap file RGB Channel Buffer Write RGB Channel Buffer Write Populates Block RAMs Populates Block RAMs Control Register Write Control Register Write Initializes Registers Initializes Registers

8 Project Status What was accomplished What was accomplished Processing BMP images using application code Processing BMP images using application code Read/Writes to the input/output image buffers Read/Writes to the input/output image buffers Communicating control data to the compressor Communicating control data to the compressor What was not completed What was not completed Communication of control data from the compressor Communication of control data from the compressor Evaluation of hardware acceleration Evaluation of hardware acceleration

9 Improvements/Suggestions Shorten design cycle Shorten design cycle Improve simulation test bench Improve simulation test bench More test corners need to be verified before running through backend flow More test corners need to be verified before running through backend flow Improve on-chip instrumentation Improve on-chip instrumentation Debug state registers can be interfaced for non-real time debugging Debug state registers can be interfaced for non-real time debugging On-chip instrumentation tools like Chipscope Pro can be used On-chip instrumentation tools like Chipscope Pro can be used Investigate usage of on-board memory Investigate usage of on-board memory Develop a linux device driver interface Develop a linux device driver interface Evaluate performance improvement due to JPEG compressor Evaluate performance improvement due to JPEG compressor Start early! Start early!


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