1. WaitLess*: Presentation #5 Team M2: Jared Dubin Terry Garove Alex Runas Manager: Panchalam Ramanujan Overall Project Objective: Table/bar service interface controller chip 10/10/2007 Schematic

2. Project Status Design proposal – complete Architecture - complete Name – provisional, debated Size estimates/basic floorplan - complete RTL / Behavioral - complete Structural – complete Schematic – complete Component layout – incomplete Functional block layout – incomplete Functional block LVS - incomplete

3. Design Decisions: - Decisions have mostly been made by this point, but… - Flip-flop has been the topic of a lot of discussion, over how to guarantee expected functionality and timing without increasing size drastically - SRAM pre-charge transistors added to attempt to improve response - Array multiplier is gigantic, but probably not a lot of room for improvement in the design itself, so we must look to its components: - Full adder blocks currently implemented as mirror adders, though we have no way to put the inverted outputs to practical use - SRAM final dimensions still in discussion, as we’ve heard both encouraging and discouraging things about our current plan - Here are some pictures, I hope you like them all:

4. Flip-flop schematic of the day:

5. Flip-flop simulation results:

6. Multiplier Schematic, as seen from space:

7. Some Promising Multiplier Simulations:

9. SRAM revised:

10. SRAM simulated:

11. Issues/Concerns: -Cadence is still not working for all of us; Jared can’t simulate his precious SRAM! - Flip-flops might not be finalized, as there is still some concern over their timing (though simulations have helped to relieve this) - Is the SRAM performing as well as we would like? - Drop-off over SRAM/decoder wires may be significant, we are considering alternate dimensions