1. Chapter 6

3. (1)Long cycle time (2)Idle transistors

4. Notice: Cycle time 200, even though some stages shorter

5. Need registers between stages, just as in multi-cycle version (discuss each of the five stages)

6. Structural hazard: Trying to use same hardware to do two different things at once Need separate instruction And data memories Need more than one ALU

7. Data hazard: Data from previous instruction not “ready” to be used by next instruction $s0 needed here, but not written until here Solutions??? $s0 still here When needed here

8. Solution #1: Stall

9. Solution #2: Data forwarding: Use data before it’s written

10. Control Hazard: Making decisions based on uncomputed data When do we know whether we’ll branch? So, what instruction do we load next?

11. One solution: Stall We’ll discuss better solutions later