1. ECE 667 - Synthesis & Verification - Lecture 0 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits VLSI Design Styles

2. ECE 667 - Synthesis & Verification - Lecture 0 2 Implementation Choices Custom Standard Cells Compiled Cells Macro Cells Cell-based Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Array-based Semicustom Digital Circuit Implementation Approaches

3. ECE 667 - Synthesis & Verification - Lecture 0 3 Cell-based Design (or standard cells) Routing channel requirements are reduced by presence of more interconnect layers

4. ECE 667 - Synthesis & Verification - Lecture 0 4 Standard Cell Layout Methodology – 1980s signals Routing channel V DD GND

5. module example(clk, a, b, c, d, f, g, h) input clk, a, b, c, d, e, f; output g, h; reg g, h; always @(posedge clk) begin g = a | b; if (d) begin if (c) h = a&~h; else h = b; if (f) g = c; else a^b; end else if (c) h = 1; else h ^b; end endmodule Specification d a b e f c 0 h g clk Logic Extraction Synthesis Flow a multi-stage process Technology-Independent Optimization f g0 h1 a c e g1 h3 h5 H G b d Technology-Dependent Mapping f d b e a c clk h H G g

7. ECE 667 - Synthesis & Verification - Lecture 0 7 Intel Pentium (IV) microprocessor

8. ECE 667 - Synthesis & Verification - Lecture 0 8 Pre-diffused (Gate Arrays) Pre-wired (FPGA's) Array-based Array based design

9. ECE 667 - Synthesis & Verification - Lecture 0 9 Gate Array — Sea-of-gates Uncommited Cell Committed Cell (4-input NOR)

10. ECE 667 - Synthesis & Verification - Lecture 0 10 Sea-of-gate Primitive Cells Using oxide-isolationUsing gate-isolation

11. ECE 667 - Synthesis & Verification - Lecture 0 11 Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K (0.6  m CMOS) Courtesy LSI Logic

12. ECE 667 - Synthesis & Verification - Lecture 0 12 2-input mux as programmable logic block F A0 B S 1 Configuration ABSF= 0000 0X1X 0Y1Y 0YXXY X0Y Y0X Y1XX 1 Y 10X 10Y 1111 X Y

13. ECE 667 - Synthesis & Verification - Lecture 0 13 Logic Cell of Actel Fuse-Based FPGA

14. ECE 667 - Synthesis & Verification - Lecture 0 14 Look-up Table Based Logic Cell

15. ECE 667 - Synthesis & Verification - Lecture 0 15 LUT-Based Logic Cell Courtesy Xilinx D 4 C 1....C 4 x xxxxx D 3 D 2 D 1 F 4 F 3 F 2 F 1 Logic function of xxx Logic function of xxx Logic function of xxx xx 4 x xx xxxx H P Bits control Bits control Multiplexer Controlled by Configuration Program x x x x xx x xxxx x xx xxxx xx x x Xilinx 4000 Series Figure must be updated

16. ECE 667 - Synthesis & Verification - Lecture 0 16 Array-Based Programmable Wiring Input/output pinProgrammed interconnection Interconnect Point Horizontal tracks Vertical tracks Cell

17. ECE 667 - Synthesis & Verification - Lecture 0 17 Mesh-based Interconnect Network Switch Box Connect Box Interconnect Point Courtesy Dehon and Wawrzyniek

18. ECE 667 - Synthesis & Verification - Lecture 0 18 Transistor Implementation of Mesh Courtesy Dehon and Wawrzyniek

19. ECE 667 - Synthesis & Verification - Lecture 0 19 Altera MAX From Smith97

20. ECE 667 - Synthesis & Verification - Lecture 0 20 Altera MAX Interconnect Architecture row channelcolumn channel LAB Courtesy Altera Array-based (MAX 3000-7000) Mesh-based (MAX 9000)