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MICE Target Report Chris Booth (for target team) Sheffield 7 th May 2009
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Chris BoothUniversity of Sheffield 2 New MICE Targets Major redesign of: Shaft Stator housing Control system Ancillaries (gate valve etc) Some delays: Materials Companies capable of accurate machining Now resolved Weekly target phone meetings (Sheffield, Imperial, RAL, Oxford). Target workshop (at Imperial) tomorrow.
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Chris BoothUniversity of Sheffield 3 New MICE Targets Critical item: target shaft Design completed Tubular lower plus cylindrical upper sections needs welded joint –Tests successful Features (inc. alignment flat) need machining –High quality surface finish; accurate straightness. –Company identified & contracted. Two different designs for the “join” –(Welding, heat-treatment, grinding) –Will produce ~6 of each and select best.
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Chris BoothUniversity of Sheffield 4 Construction Schedule Shafts:Both designs, manufacturing complete by 22 nd June DLC coating by 3 rd July Sign off7 th July Bearings:Complete by 17 th June DLC coat, sign off1 st July Stators:Coil assembly on temporary former. 1 complete in Sheffield. Parts ready for second. Vacuum tubes duenext week Fit coils, cooling jacket; stator to RAL21 st May Core components manufactured, at RAL27 th May Assemble, weld, test19 th June Two complete target assemblies ready for installationend July (For details, see Jason Tarrant.)
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Chris BoothUniversity of Sheffield 5 Installation & Commissioning Schedule (Draft! To be discussed tomorrow!) Early August (1 week): Assemble Target1: Core (stator), shaft, optics, bellows in clean area at RAL. Install in R78. Add optical, electrical, water connections. Run for ≤ 1 week (How many pulses??) Infrastructure planning – finalise tomorrow. In parallel, assemble Target2. Install Target2 in R78. Run as demonstrator. Transfer Target1 to ISIS, install in August shutdown.
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Chris BoothUniversity of Sheffield 6 Target Control System First phase is to duplicate present functionality using FPGA sytem, with PC-based user interface accessed over USB. Development underway (Sheffield/IC) Duplicate interface boards (copies of present system) complete. –Incurred slight delay. VHDL framework almost complete. FPGA interface PCBs under test. Firmware nearly complete. Should be ready for end July, for test and installation in ISIS. Existing system (in MICE LCR) is an acceptable short-term fallback.
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