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S. RossEECS 40 Spring 2003 Lecture 22 Inside the CMOS inverter, no I D current flows through transistors when input is logic 1 or logic 0, because the.

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Presentation on theme: "S. RossEECS 40 Spring 2003 Lecture 22 Inside the CMOS inverter, no I D current flows through transistors when input is logic 1 or logic 0, because the."— Presentation transcript:

1 S. RossEECS 40 Spring 2003 Lecture 22 Inside the CMOS inverter, no I D current flows through transistors when input is logic 1 or logic 0, because the NMOS transistor is cutoff for logic 0 (0 V) input the PMOS transistor is cutoff for logic 1 (V DD ) input current through the “turned on” transistor has nowhere to go if next stage consists of transistor gates D S V DD D S V OUT1 V IN D S V DD D S V OUT2 CMOS LOGIC

2 S. RossEECS 40 Spring 2003 Lecture 22 V OUT I D(N) (= -I D(P) ) V DD X V OUT I D(N) (= -I D(P) ) V DD X NMOS transistor cutoff (since V GS(N) = V IN = 0 V) “acts as open circuit” PMOS transistor “on” (V GS(P) = V IN – V DD = -V DD ) but I D(P) = 0 A => V DS(P) = 0 V PMOS transistor cutoff (V GS(P) = V IN – V DD = 0 V) “acts as open circuit” NMOS transistor “on” (V GS(N) = V IN = V DD ) but I D(N) = 0 A => V DS(N) = 0 V V IN = 0 V V IN = V DD

3 S. RossEECS 40 Spring 2003 Lecture 22 There is a simpler model for the behavior of transistors in a CMOS logic circuit, which applies when the input to the logic circuit is fully logic 0 or fully logic 1. D G S We can use the model to quickly determine the logical operation of a CMOS circuit (but we cannot use it to find circuit currents or voltages that will occur for mid-range input voltages). V GS = 0 V V GS = V DD (for NMOS) V GS = -V DD (for PMOS) D G S Each transistor will be in one of these two situations! EASY MODEL FOR LOGIC ANALYSIS

4 S. RossEECS 40 Spring 2003 Lecture 22 V OUT V DD V IN = V DD V OUT V DD V IN = 0 V REVISIT CMOS INVERTER WITH SIMPLE LOGIC MODEL Fill in the switch positions below…

5 S. RossEECS 40 Spring 2003 Lecture 22 V DD A F B S S S S PMOS 1 NMOS 1 PMOS 2 NMOS 2 CMOS NAND

6 S. RossEECS 40 Spring 2003 Lecture 22 F V DD A = 0V S S S S Verify the logical operation of the CMOS NAND circuit: B = 0V F V DD A = 0V S S S S B = V DD

7 S. RossEECS 40 Spring 2003 Lecture 22 F V DD A = V DD S S S S Verify the logical operation of the CMOS NAND circuit: B = 0V F V DD A = V DD S S S S B = V DD

8 S. RossEECS 40 Spring 2003 Lecture 22 V DD A F B S S S S PMOS 1 NMOS 1 PMOS 2 NMOS 2 CMOS NOR

9 S. RossEECS 40 Spring 2003 Lecture 22 Verify the logical operation of the CMOS NOR circuit: V DD A = 0V F S S S S V DD F S S S S B = 0V A = 0V B = V DD

10 S. RossEECS 40 Spring 2003 Lecture 22 Verify the logical operation of the CMOS NOR circuit: V DD A = V DD F S S S S V DD F S S S S B = 0V A = V DD B = V DD

11 S. RossEECS 40 Spring 2003 Lecture 22 Notice that when NMOS transistors are “on” (when V GSN = V DD ) V DSN is shorted by switch, helping connect output to ground. The NMOS transistor functions as a pull-down device; when active, it brings the output to 0 V. When PMOS transistors are “on” (when V GSP = -V DD ) V DSP is shorted by switch, helping connect output to V DD. The PMOS transistor functions as a pull-up device; when active, it brings the output to V DD. In our logic circuits, the NMOS transistor sources are connected to ground, and the PMOS sources are connected to V DD. PULL-UP AND PULL-DOWN DEVICES

12 S. RossEECS 40 Spring 2003 Lecture 22 A F B S S S S PMOS 1 NMOS 1 PMOS 2 NMOS 2 V DD In reality, the pull-up devices must have some V DS voltage and current flow to bring the output high since natural capacitance must be charged. Similarly, the pull-down devices must have some V DS voltage and current flow to bring the output to ground since natural capacitance must be discharged. LIMITATIONS OF SWITCH MODEL Preview of next class: This is GATE DELAY.

13 S. RossEECS 40 Spring 2003 Lecture 22 A = V DD F S S S S PMOS 1 NMOS 1 PMOS 2 NMOS 2 V DD B = V TH(N) +  LIMITATIONS OF SWITCH MODEL Suppose one needed to fully analyze the circuit for intermediate input voltages. Requires many equations, many unknowns. But, we can at least guess the modes.

14 S. RossEECS 40 Spring 2003 Lecture 22 A = V DD S S S S PMOS 1 NMOS 1 PMOS 2 NMOS 2 V DD B = V TH(N) +  Assume V DD around 5 V, V TH(N) around 1 V, V TH(P) around -1 V,  around 0.5 V. PMOS 1 cutoff NMOS 1 barely on (V DS(N2) ≥ 0) => saturation NMOS 2 fully on, but NMOS 1 limits I D to small value => triode PMOS 2 on, but NMOS 1 and PMOS 1 make I D small => triode

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