1. Chap.10 Digital Integrated Circuits

2. Content  10-1 Introduction  10-2 Feature  10-3 Feature of BJT  10-4 RTL and DTL  10-5 TTL  10-6 ECL  10-7 MOS  10-8 CMOS  10-9 MOS transmission gate

3. 10-1 Introduction — Logic IC ASIC: Application Specific Integrated Circuits ASIC: Application Specific Integrated Circuits

4. 10-1 Introduction  IC digital logic families –RTL （ Resistor-transistor logic ） –DTL （ Diode-transistor logic ） –TTL （ Transistor -transistor logic ） –ECL （ Emitter-coupled logic ） –MOS （ Metal-oxide semiconductor ） –CMOS （ Complementary Metal-oxide semiconductor ）

5. Positve logic and Negative logic Positive logic: H is set to be binary 1 Negative logic: L is set to be binary 1

6. 10-2 Feature  The feature to be concerned of IC logic families: –fan-out The no. of standard loads can be connected to the output of the gate without degrading its normal operation Sometimes the term loading is used –Power dissipation The power needed by the gate Expressed in mW –Propagation delay The average transition-delay time for the signal to propagate from input to output when the binary signal changes in value –Noise margin The unwanted signals are referred to as noise Noise margin is the maximum noise added to an input signal of a digital circuit that does not cause an undesirable change in the circuit output

7. Computing fan-out

8. William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Computing fan-out ( High-level output)

9. William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Computing fan-out ( Low-level output)

10. Power dissipation

11. Propagation delay 50% V H For standard TTL

12. Other delay times –Rise Time from 10% up to 90% level –Fall Time from 90% down to 10% level

13. Noise margin

14. High-state noise margin=0.4 Low-state noise margin=0.4

15. 10-3 Feature of BJT  BJT – npn or pnp –Si or Ge –Si is used mainly –npn is most popular

16. Table 10-1 Typical npn Transistor Parameters RegionV BE (V)V CE (V)Current Relation Cutoff< 0.6Open circuit I B =I C =0 Active0.6-0.7> 0.8I C =h FE I B Saturation0.7-0.80.2I B ≥I C /h FE

17. Feature of npn-type BJT

18. Diode – symbol and characteristic

19. 10-4 RTL and DTL circuits  RTL –Resistor TL –L: 0.2V, H: 1~3.6V  DTL –Diode TL –L: 0.2V, H: 4~5V

20. RTL--NOR

21. DTL--NAND

22. Modified DTL

23. 10-5 Transistor-Transistor Logic (TTL)  The original basic TTL gate was a slight improvement over the DTL gate.  There are several TTL subfamilies or series of the TTL technology.  Eight TTL series appear in Table 10-2.  Has a number start with 74 and follows with a suffix that identifies the series type, e.g 7404, 74S86, 74ALS161.  Three different types of output configurations: –1. open-collector output –2. Totem-pole output –3. Three-state (or tristate) output

24. Open-collector TTL Gate

25. Wired-AND of Two Open-Collector

26. Open-Collector Gates Forming a Common Bus Line In this case Y = ?

27. TTL Gate with Totem-Pole Output

28. Schottky TTL Gate

29. Three-state TTL Gate

30. 10-6 Emitter-Coupled Logic (ECL)  Nonsaturated digital logic family  Propagation rate as low as 1-2ns  Used mostly in high speed circuits  Noise immunity and power dissipation is the worst of all logic families.  High level -0.8V, Low level -1.8V  Including –Differential input amplifier –Internal temperature and voltage compensated bias network –Emitter-follower outputs

31. ECL Basic Gate

32. Graphic Symbols of ECL Gates