1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 426 - VLSI System Design Lecture 7 - Synchronizers and Metastability February 19, 2003

2. 2/19/03ECE 426 - Lecture 72 Announcements  No class Mon. 2/17 due to blizzard

3. 2/19/03ECE 426 - Lecture 73 Where we are...  Last Time  Verilog Coding Guidelines  Today  More about Synchronizers and Metastability

4. 2/19/03ECE 426 - Lecture 74 Synchronizer Review  Key idea: make sure inputs don’t change at a “bad time” in sequential circuits in1 in2 in3 00 1001 in1’ in1 0110 clk in1 NS 11 transient

5. 2/19/03ECE 426 - Lecture 75 Adding Synchronizers  Add a D Flip-Flop on each asynchronous input  Synchronize each input only once  Don’t use dynamic flip-flops (we’ll discuss why)  Q: What happens when set up & hold time violated? DQ clk in2_a in2_s DQ in1_a in1_s

6. 2/19/03ECE 426 - Lecture 76 Metastability: When bad things happen to good synchronizers Q: What happens when t su / t h constraints violated? A: It depends, but there are three scenarios 1.Circuit correctly records new D value 1.Circuit retains old D value for an extra cycle 3.Metastability - “stuck” between legal 0 and 1 until it “resolves” CLK D Q1 Q2 Q3 t su thth t clk-q Resolution Time t r

7. 2/19/03ECE 426 - Lecture 77 Metastability - Review from last semester  Two stable states  V o1 =L, V o2 =H  V o1 =H, V o2 =L  One metastable state  V o1 = V o2  Ugly characteristic: unbounded recovery time t r Graphic source: J. Rabaey, Digital Integrated Circuits, © Prentice-Hall, 1996 Metastable point

8. 2/19/03ECE 426 - Lecture 78 Metastability - “Ball on the Hill” Analogy  Sides of hill = stable states  Top of hill = metastable state  Any small “push” (e.g., noise) will move the ball off the hill and into a stable state

9. 2/19/03ECE 426 - Lecture 79 Metastability - Bad News / Good News  Bad news  Metastability is unavoidable  Recovery time is theoretically unbounded  Good news  Can empirically measure recovery times  Can use statistics from recovery times to make failure probability arbitrarily small

10. 2/19/03ECE 426 - Lecture 710 Measuring Metastability Characteristics  Intentionally cause metastability many times  Measure recovery for each occurrence  Fit recovery times to exponential function t clk-q Number Of Occurrences Recovery Time

11. 2/19/03ECE 426 - Lecture 711 Designing with Metastability  A synchronizer design at a given clock period provides a fixed amount of resolution time tr  Definition: a synchronization failure occurs when actual recovery time t r-actual > t r  For a given flip-flop, the mean time between failure (MTBF) is given by the formula f clk - System clock freq. a - asynchronous input rate of change.  - empirically derived constant T o - empirically derived constant t r - time available for resolution

12. 2/19/03ECE 426 - Lecture 712 Determining Resolution Time t r  Must leave time for system to respond properly after resolution t r = t clk - t su - t prop Comb. Logic D Q D Q clk t prop t su

13. 2/19/03ECE 426 - Lecture 713 Resolution Time Example  Suppose that  fclk = 100MHz (t clk = 10ns)  a = 1MHz  t prop = 6.7ns  t su = 1ns  Calculate t r :  t r = t clk - t su - t prop  t r = 10ns - 6.7ns -1ns = 2.3ns Comb. Logic D Q D Q clk t prop =6.7ns t su =1ns

14. 2/19/03ECE 426 - Lecture 714 MTBF Calculation Example  “Typical” values for a 0.25µm ASIC library flip-flop   = 0.31ns  T o = 9.6as “a” = 10 -18  t r = 2.3ns  MTBF = 20.1 days - unacceptable!

15. 2/19/03ECE 426 - Lecture 715 What happens if we halve f clk ?  Suppose that  fclk = 50MHz (t clk = 20ns)  a = 1MHz  t prop = 6.7ns  t su = 1ns  Calculate t r and MTBF:  t r = t clk - t su - t prop  t r = 20ns - 6.7ns -1ns = 12.3ns  MTBF = 5.7 X 10 28 seconds = 1.8 X 10 21 years

16. 2/19/03ECE 426 - Lecture 716 Alternative: Dual-Stage Synchronizer  Increased value for t r : t r = t clk - t su - t pr t r = 10ns - 1ns = 9ns Comb. Logic D Q D Q clk t prop t su D Q

17. 2/19/03ECE 426 - Lecture 717 Dual-Stage MTBF Calculation  “Typical” values for a 0.25µm ASIC library flip-flop   = 0.31ns  T o = 9.6as “a” = 10 -18  t r = 9ns  MTBF = ?

18. 2/19/03ECE 426 - Lecture 718 Other Synchronizer Alternatives  Metastability-hardened SYNC flip-flops provided by ASIC library  Multiple-Stage Synchronizers  Reduced-Clock Synchronizers

19. 2/19/03ECE 426 - Lecture 719 What to Do About Metastability  Start with simple synchronizer (single flip-flop)  Calculate MTBF for your system  Decide if it's acceptable  If not, use faster flip-flop  OR different design:  Two-stage flip-flop  Reduced-clock synchronizers

20. 2/19/03ECE 426 - Lecture 720 Back to Synchronous Logic Guidelines  See Lecture 6 Notes

21. 2/19/03ECE 426 - Lecture 721 Architecture Design (Ch. 8)  Goal: design high-level organization of chip  Organization is usually described using the register transfer abstraction  Describes system as connected network of Registers Combinational logic  Treats overall design as a large sequential circuit  Specifies system function on a cycle-by-cycle basis  Used as an input specification for logic synthesis (e.g., Synopsys) tools

22. 2/19/03ECE 426 - Lecture 722 The Datapath-Controller Abstraction  A higher-level description of chip organization  Key idea: break up design into two parts:  Datapath- components that manipulate data  Controller - FSM that controls datapath modules

23. 2/19/03ECE 426 - Lecture 723 Steps in Architecture Design  Propose data unit components  functions performed  data inputs / outputs  control inputs - perform operation when asserted  status outputs - condition info for control unit  Design control-unit FSM  Respond to ext. inputs, status values from data unit  Generate control signals to drive data unit, external outputs  Control-Unit Representations Traditional "bubble and arrow" state diagram Algorithmic State Machine (ASM) diagrams

24. 2/19/03ECE 426 - Lecture 724 Coming Up  Next Lab: Verifying Sequential Circuits  ASM Diagrams  Controller / Datapath Design Examples

25. 2/19/03ECE 426 - Lecture 725

26. 2/19/03ECE 426 - Lecture 726

27. 2/19/03ECE 426 - Lecture 727 Verification Plan  Definition: A Specification of the Verification Effort  Prerequisite: Specification document for design  Defnining Success - Must Identify  Features which must be exercisedunder which conditions  Expected Response

28. 2/19/03ECE 426 - Lecture 728 Levels of Verification  Board  System / Subsystem  ASIC / FPGA  Unit / Subunit

29. 2/19/03ECE 426 - Lecture 729 Levels of Verification  Connectivity  Transaction / Cooperative Data Flow  Functionality  Ad Hoc  Designer verifies basic functionality

30. 2/19/03ECE 426 - Lecture 730 Levels of Verification - Notes  Stable interfaces required at each level of granularity

31. 2/19/03ECE 426 - Lecture 731 Rules for Style  Optimize the Right Thing  Good Comments Improve Maintainability  Encapsulation Hides Implementation Details

32. 2/19/03ECE 426 - Lecture 732 Lab 3 Overview  Self-checking testbench for generic counter  Identify important features  Create conditions that test these features  Check conditions  Write message when error occurs  “Insert” errors to demonstrate when self-check fails  Test for varying values of N (2, 8, 10, 16)

33. 2/19/03ECE 426 - Lecture 733 System Design Issues  ASM Diagrams  Synchronization & Metastability  Handshaking  Working with Multiple Clocks