1. Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT Victor Khomenko, Maciej Koutny, and Alex Yakovlev University of Newcastle upon Tyne

2. 2 Talk Outline Introduction  Asynchronous circuits  Logic synthesis based on state graphs  State graphs vs. net unfoldings Logic synthesis based on net unfoldings Experimental results Future work

3. 3 Asynchronous Circuits Asynchronous circuits – no clocks: Low power consumption Average-case rather than worst-case performance Low electro-magnetic emission Modularity – no problems with the clock skew  Hard to synthesize  The theory is not sufficiently developed  Limited tool support

4. 4 Example: VME Bus Controller lds-d-ldtack-ldtack+ dsr-dtack+d+ dtack-dsr+lds+ Device VME Bus Controller lds ldtack d Data Transceiver Bus dsr dtack

5. 5 Example: CSC Conflict dtack-dsr+ dtack-dsr+ dtack-dsr+ 00100 ldtack- 00000 10000 lds- 01100 01000 11000 lds+ ldtack+ d+ dtack+dsr- d- 01110 01010 11010 011111111111011 11010 10010 M’’M’

6. 6 Example: Enforcing CSC dtack-dsr+ dtack-dsr+ dtack-dsr+ 001000 ldtack- 000000 100000 lds- 011000 010000 110000 lds+ ldtack+ d+ dtack+dsr- d- 011100 010100 110100 011111111111110111 110101 100101 011110 csc+ csc- 100001 M’’M’

7. 7 Example: Deriving Equations CodeNxt dtack Nxt lds Nxt d Nxt csc 001000 000000 100000 100001 011000 010000 110000 100101 011100 010100 110100 110101 011110 011111 111111 110111 00000000000011110000000000001111 00010001000111110001000100011111 00000000000101110000000000010111 00110001000100110011000100010011 Eqnd d  csccsc  ldtack dsr  (  ldtack  csc)

8. 8 Example: Resulting Circuit Device d Data Transceiver Bus dsr dtack lds ldtack csc

9. 9 State Graphs: Relatively easy theory Many efficient algorithms  Not visual  State space explosion problem State Graphs vs. Unfoldings

10. 10 State Graphs vs. Unfoldings Unfoldings: Alleviate the state space explosion problem More visual than state graphs Proven efficient for model checking  Quite complicated theory  Not sufficiently investigated  Relatively few algorithms

11. 11 Complex-gate synthesis State Graphs vs. Unfoldings SGUnf Checking consistency Checking semi-modularity Deadlock detection Checking CSC Enforcing CSC Deriving equations Technology mapping DATE’03 ACSD’04 DATE’02 & ACSD’03

12. 12 Synthesis using unfoldings Outline of the algorithm: for each output signal z compute (minimal) supports of z for each ‘promising’ support X compute the projection of the set of reachable encodings onto X sorting them according to the corresponding values of Nxt z apply Boolean minimization to the obtained ON- and OFF-sets choose the best implementation of z

13. 13 CSC z property The CSC property: the next-state function of every output signal is a well-defined Boolean function of encoding of current state, i.e., all the signals can be used in its support The CSC z property: Nxt z is a well-defined Boolean function of encoding of current state; again, all the signals can be used in its support The CSC z property: Nxt z is a well-defined Boolean function of projection of the encoding of the current state on set of signals X; i.e., X is a support X X

14. 14 CSC z conflicts States M’ and M’’ are in CSC z conflict if  Code x (M’)=Code x (M’’) for all x  X, and  Nxt z (M’)  Nxt z (M’’) Nxt z can be expressed as a Boolean function with support X iff there are no CSC z conflicts X X X

15. 15 Example: CSC z conflict X dtack-dsr+ dtack-dsr+ dtack-dsr+ 001000 ldtack- 000000 100000 lds- 011000 010000 110000 lds+ ldtack+ d+ dtack+dsr- d- 011100 010100 110100 011111111111110111 110101 100101 011110 csc+ csc- 100001 Nxt csc (M’)=1 Nxt csc (M’’)=0 M’’ M’ X={dsr, ldtack}

16. 16 Example: CSC z conflict in unfolding lds- d- ldtack- ldtack+ dsr- dtack+ d+ dtack- dsr+lds+ csc+ dsr+ e1e1 e2e2 e3e3 e4e4 e5e5 e6e6 e7e7 e9e9 e 11 e 14 e 10 e8e8 X dsrldtackdtackldsdcsc Code(C’)110101 Code(C’’) 110000 csc+csc- e 12 e 13 Nxt csc = dsr  (  ldtack  csc) X Nxt csc (C’)=1  Nxt csc (C’’)=0 C’C’’

17. 17 Computing supports Using unfoldings, it is possible to construct a Boolean formula CSC z (X,…) such that CSC z (X,…)[Y/X] is satisfiable iff Y is not a support The projection of the set of satisfying assignments of CSC z (X,…) onto X is the set of all non-supports of z (it is sufficient to compute the maximal elements of this projection) The set of supports can then be computed as { Y | Y  X, for all maximal non-supports X }

18. 18 Outline of the algorithm for each output signal z compute (minimal) supports of z for each ‘promising’ support X compute the projection of the set of reachable encodings onto X sorting them according to the corresponding values of Nxt z apply Boolean minimization to the obtained ON- and OFF-sets choose the best implementation of z Need to know how to compute projections!

19. 19 Example: projections  =(a  b)(  a   b)(c  d  e) abcde 01001 01010 01011 01100 01101 01110 01111 10001 10010 10011 10100 10101 10110 10111 a  b Proj {a,b,c}  abc 010 011 100 101 max Proj {a,b,c}  abc 011 101 min Proj {a,b,c}  abc 010 100

20. 20 Computing projections 0100101001 Proj {a,b,c}  abcde 0110001100 1000110001 1010010100 UNSAT (a  b  c) a  b  =(a  b)(a  b)(c  d  e) Incremental SAT

21. 21 Optimizations Triggers belong to every support – significantly improves the efficiency Further optimizations are possible for certain net subclasses, e.g. unique-choice nets

22. 22 Experimental Results Unfoldings of STGs are almost always small in practice and thus well-suited for synthesis Huge memory savings Dramatic speedups Every valid speed-independent solution can be obtained using this method, so no loss of quality We can trade off quality for speed (e.g. consider only minimal supports): in our experiments, the solutions are the same as Petrify’s (up to Boolean minimization) Multiple implementations produced

23. 23 Future Work SGUnf Checking consistency Checking semi-modularity Deadlock detection Checking CSC Enforcing CSC Deriving equations Technology mapping Timing assumptions?

24. 24 Thank you! Any questions?