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Defect-tolerant FPGA Switch Block and Connection Block with Fine- grain Redundancy for Yield Enhancement Anthony J. YuGuy G.F. Lemieux August 25, 2005.

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Presentation on theme: "Defect-tolerant FPGA Switch Block and Connection Block with Fine- grain Redundancy for Yield Enhancement Anthony J. YuGuy G.F. Lemieux August 25, 2005."— Presentation transcript:

1 Defect-tolerant FPGA Switch Block and Connection Block with Fine- grain Redundancy for Yield Enhancement Anthony J. YuGuy G.F. Lemieux August 25, 2005

2 FPL'05 - Presentation 2 Outline Introduction and Motivation Previous Approaches Fine-grain Redundancy ResultsConclusions

3 FPL'05 - Presentation 3 Introduction and Motivation Scaling introduces new types of defects Number of defects expected to increase as chip density increases –As a result, chip yield is on the decline FPGAs are mostly interconnect To improve yield (and revenue), we must tolerate multiple interconnect defects

4 FPL'05 - Presentation 4 Previous Approaches Defect-tolerance is one method to minimize impact of manufacturing defects Two approaches taken by industry: avoid the defective resources (Xilinx EasyPath) or make the defective resources inaccessible (Altera) Past attempts either did not scale well, required too much reprogramming time or affected signal timing

5 FPL'05 - Presentation 5 Objective Problem –FPGA yield is on decline because of aggressive technology scaling Important objectives to improve yield: –Tolerate interconnect defects (dominates area) –Tolerate multiple defects (future trend) –Preserve timing (no timing re-verification) –Fast correction time (production use)

6 FPL'05 - Presentation 6 Fine-grain Redundancy (FGR) – Defect Avoidance by Shifting

7 FPL'05 - Presentation 7 Island-style FPGA

8 FPL'05 - Presentation 8 Directional Switch Block

9 FPL'05 - Presentation 9 Directional Switch Block

10 FPL'05 - Presentation 10 Defect-tolerant Switch Block

11 FPL'05 - Presentation 11 Switch Implementation Options

12 FPL'05 - Presentation 12 Defect Avoidance - Example 1

13 FPL'05 - Presentation 13 Defect Avoidance - Example 2

14 FPL'05 - Presentation 14 Results AreaDelay Area Delay Product YieldSummary

15 FPL'05 - Presentation 15 Area Results

16 FPL'05 - Presentation 16 Delay Results

17 FPL'05 - Presentation 17 Area-Delay Product

18 FPL'05 - Presentation 18 Yield - 1 * Assumes all bridging defects

19 FPL'05 - Presentation 19 Yield - 2

20 FPL'05 - Presentation 20 Summary

21 FPL'05 - Presentation 21 Conclusion FGR meets desired objectives: –Tolerates multiple randomly distributed defects –Defect correction does not perturb timing –Tolerates an increasing number of defects as array size increases –Correction can be applied quickly FGR has different implementation options –Trade-offs between yield, area and delay can be made

22 Thank you! anthonyy@ece.ubc.ca

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