1. CSE331 W02.1Irwin&Li 2006 PSU CSE 331 Computer Organization and Design Fall 2006 Adaptado a DSD. R. Pereira Section 1: Mary Jane Irwin (www.cse.psu.edu/~mji)www.cse.psu.edu/~mji Section 2: Feihui Li (www.cse.psu.edu/~feli )www.cse.psu.edu/~feli Course material on ANGEL: cms.psu.edu [ adapted from D. Patterson slides ]

2. CSE331 W02.2Irwin&Li 2006 PSU Review: Execute Cycle Processor Control Datapath Memory contents Reg #4 ADD contents Reg #2 results put in Reg #2 The datapath executes the instructions as directed by control 000000 00100 00010 0001000000100000 Memory stores both instructions and data Devices Input Output Network

3. CSE331 W02.3Irwin&Li 2006 PSU Review: Processor Organization  Control needs to have circuitry to l Decide which is the next instruction and input it from memory l Decode the instruction l Issue signals that control the way information flows between datapath components l Control what operations the datapath’s functional units perform l Execute instructions - functional units (e.g., adder) and storage locations (e.g., register file) l Interconnect the functional units so that the instructions can be executed as required l Load data from and store data to memory  Datapath needs to have circuitry to Fetch DecodeExec

4. CSE331 W02.4Irwin&Li 2006 PSU Assembly Language Instructions  The language of the machine l Want an ISA that makes it easy to build the hardware and the compiler while maximizing performance and minimizing cost  Stored program (von Neumann) concept l Instructions are stored in memory (as is the data)  Our target: the MIPS ISA l similar to other ISAs developed since the 1980's l used by Broadcom, Cisco, NEC, Nintendo, Sony, … Design goals: maximize performance, minimize cost, reduce design time (time-to-market), minimize memory space (embedded systems), minimize power consumption (mobile systems)

5. CSE331 W02.5Irwin&Li 2006 PSU RISC - Reduced Instruction Set Computer  RISC philosophy l fixed instruction lengths l load-store instruction sets l limited number of addressing modes l limited number of operations  MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC …  Instruction sets are measured by how well compilers use them as opposed to how well assembly language programmers use them  CISC (C for complex), e.g., Intel x86

6. CSE331 W02.6Irwin&Li 2006 PSU The Four Design Principles 1. Simplicity favors regularity. 2. Smaller is faster. 3. Make the common case fast. 4. Good design demands good compromises.

7. CSE331 W02.7Irwin&Li 2006 PSU MIPS Arithmetic Instruction  MIPS assembly language arithmetic statement add$t0, $s1, $s2 sub$t0, $s1, $s2  Each arithmetic instruction performs only one operation  Each arithmetic instruction specifies exactly three operands destination  source1 op source2 l Operand order is fixed (the destination is specified first)  The operands are contained in the datapath’s register file ( $t0, $s1, $s2 )

8. CSE331 W02.8Irwin&Li 2006 PSU MIPS Arithmetic Instruction  MIPS assembly language arithmetic statement add$t0, $s1, $s2 sub$t0, $s1, $s2  Each arithmetic instruction performs only one operation  Each arithmetic instruction specifies exactly three operands destination  source1 op source2 l Operand order is fixed (the destination is specified first)  The operands are contained in the datapath’s register file ( $t0, $s1, $s2 )

9. CSE331 W02.9Irwin&Li 2006 PSU Compiling More Complex Statements  Assuming variable b is stored in register $s1, c is stored in $s2, and d is stored in $s3 and the result is to be left in $s0, what is the assembler equivalent to the C statement h = (b - c) + d

10. CSE331 W02.10Irwin&Li 2006 PSU Compiling More Complex Statements  Assuming variable b is stored in register $s1, c is stored in $s2, and d is stored in $s3 and the result is to be left in $s0, what is the assembler equivalent to the C statement h = (b - c) + d sub$t0, $s1, $s2 add$s0, $t0, $s3

11. CSE331 W02.11Irwin&Li 2006 PSU MIPS Register File  Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath’s register file l Thirty-two 32-bit registers -Two read ports -One write port  Registers are l Fast -Smaller is faster & Make the common case fast l Easy for a compiler to use -e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order l Improves code density -Since register are named with fewer bits than a memory location  Register addresses are indicated by using $

12. CSE331 W02.12Irwin&Li 2006 PSU MIPS Register File  Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath’s register file l Thirty-two 32-bit registers -Two read ports -One write port  Registers are l Fast -Smaller is faster & Make the common case fast l Easy for a compiler to use -e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order l Improves code density -Since register are named with fewer bits than a memory location  Register addresses are indicated by using $ Register File src1 addr src2 addr dst addr write data 32 bits src1 data src2 data 32 locations 32 5 5 5

13. CSE331 W02.13Irwin&Li 2006 PSU 0$zero constant 0 (Hdware) 1$atreserved for assembler 2$v0expression evaluation & 3$v1function results 4$a0arguments 5$a1 6$a2 7$a3 8$t0temporary: caller saves...(callee can clobber) 15$t7 Naming Conventions for Registers 16$s0callee saves... (caller can clobber) 23$s7 24$t8 temporary (cont’d) 25$t9 26$k0reserved for OS kernel 27$k1 28$gppointer to global area 29$spstack pointer 30$fpframe pointer 31$rareturn address (Hdware)

14. CSE331 W02.14Irwin&Li 2006 PSU Registers vs. Memory  Arithmetic instructions operands must be in registers l only thirty-two registers are provided  Compiler associates variables with registers  What about programs with lots of variables? Processor Control Datapath Memory Devices Input Output Network

15. CSE331 W02.15Irwin&Li 2006 PSU Registers vs. Memory  Arithmetic instructions operands must be in registers l only thirty-two registers are provided  Compiler associates variables with registers  What about programs with lots of variables? Processor Control Datapath Memory Devices Input Output Network

16. CSE331 W02.16Irwin&Li 2006 PSU  Memory is a large, single-dimensional array  An address acts as the index into the memory array Processor – Memory Interconnections Processor Memory 32 bits ? locations read addr/ write addr read data write data 1 101 10 0 4 8

17. CSE331 W02.17Irwin&Li 2006 PSU  Memory is a large, single-dimensional array  An address acts as the index into the memory array Processor – Memory Interconnections Processor Memory 32 bits ? locations read addr/ write addr read data write data 32 2 32 Bytes (4 GB)  2 30 Words (1 GW) = 4 Bytes = 1 Word 1 101 10 0 4 8 The data stored in the memory The word address of the data

18. CSE331 W02.18Irwin&Li 2006 PSU  MIPS has two basic data transfer instructions for accessing memory (assume $s3 holds 24 10 ) lw$t0, 4($s3) #load word from memory sw$t0, 8($s3) #store word to memory  The data transfer instruction must specify l where in memory to read from (load) or write to (store) – memory address l where in the register file to write to (load) or read from (store) – register destination (source)  The memory address is formed by summing the constant portion of the instruction and the contents of the second register Accessing Memory

19. CSE331 W02.19Irwin&Li 2006 PSU  MIPS has two basic data transfer instructions for accessing memory (assume $s3 holds 24 10 ) lw$t0, 4($s3) #load word from memory sw$t0, 8($s3) #store word to memory  The data transfer instruction must specify l where in memory to read from (load) or write to (store) – memory address l where in the register file to write to (load) or read from (store) – register destination (source)  The memory address is formed by summing the constant portion of the instruction and the contents of the second register Accessing Memory 28 32

20. CSE331 W02.20Irwin&Li 2006 PSU MIPS Memory Addressing  The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register lw$t0, 4($s3) #what? is loaded into $t0 sw$t0, 8($s3) #$t0 is stored where? Memory... 0 1 0 0 DataWord Address 0 4 8 12 16 20 24... 1 0 0 0... 0 0 1 0... 0 0 0 1... 1 1 0 0... 0 1 0 1... 0 1 1 0 $s3 holds 8

21. CSE331 W02.21Irwin&Li 2006 PSU MIPS Memory Addressing  The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register lw$t0, 4($s3) #what? is loaded into $t0 sw$t0, 8($s3) #$t0 is stored where? Memory... 0 1 0 0 32 bit DataWord Address 0 4 8 12 16 20 24... 1 0 0 0... 0 0 1 0... 0 0 0 1... 1 1 0 0... 0 1 0 1... 0 1 1 0 $s3 holds 8 in location 16... 0001

22. CSE331 W02.22Irwin&Li 2006 PSU Compiling with Loads and Stores  Assuming variable b is stored in $s2 and that the base address of array A is in $s3, what is the MIPS assembly code for the C statement A[8] = A[2] - b $s3 $s3 +4 $s3 +8 $s3 +12... A[2] A[3]... A[1] A[0]

23. CSE331 W02.23Irwin&Li 2006 PSU Compiling with Loads and Stores  Assuming variable b is stored in $s2 and that the base address of array A is in $s3, what is the MIPS assembly code for the C statement A[8] = A[2] - b $s3 $s3 +4 $s3 +8 $s3 +12... A[2] A[3]... A[1] A[0] lw$t0, 8($s3) sub$t0, $t0, $s2 sw$t0, 32($s3)

24. CSE331 W02.24Irwin&Li 2006 PSU Compiling with a Variable Array Index  Assuming that the base address of array A is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement c = A[i] - b add$t1, $s3, $s3#array index i is in $s3 add$t1, $t1, $t1#temp reg $t1 holds 4*i $s4 $s4 +4 $s4 +8 $s4 +12... A[2] A[3]... A[1] A[0]

25. CSE331 W02.25Irwin&Li 2006 PSU Compiling with a Variable Array Index  Assuming that the base address of array A is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement c = A[i] - b add$t1, $s3, $s3#array index i is in $s3 add$t1, $t1, $t1#temp reg $t1 holds 4*i $s4 $s4 +4 $s4 +8 $s4 +12... A[2] A[3]... A[1] A[0] add$t1, $t1, $s4#addr of A[i] now in $t1 lw$t0, 0($t1) sub$s2, $t0, $s1

26. CSE331 W02.26Irwin&Li 2006 PSU  Small constants are used quite frequently (50% of operands in many common programs) e.g., A = A + 5; B = B + 1; C = C - 18;  Solutions? Why not? l Put “typical constants” in memory and load them l Create hard-wired registers (like $zero) for constants like 1, 2, 4, 10, … Dealing with Constants  How do we make this work?  How do we Make the common case fast !

27. CSE331 W02.27Irwin&Li 2006 PSU  Include constants inside arithmetic instructions l Much faster than if they have to be loaded from memory (they come in from memory with the instruction itself)  MIPS immediate instructions addi$s3, $s3, 4#$s3 = $s3 + 4  There is no subi instruction, can you guess why not? Constant (or Immediate) Operands

28. CSE331 W02.28Irwin&Li 2006 PSU MIPS Instructions, so far CategoryInstrExampleMeaning Arithmeticaddadd $s1, $s2, $s3$s1 = $s2 + $s3 subtractsub $s1, $s2, $s3$s1 = $s2 - $s3 add immediate addi $s1, $s2, 4$s1 = $s2 + 4 Data transfer load wordlw $s1, 32($s2)$s1 = Memory($s2+32) store wordsw $s1, 32($s2)Memory($s2+32) = $s1

29. CSE331 W02.29Irwin&Li 2006 PSU End of Lecture #3

30. CSE331 W02.30Irwin&Li 2006 PSU In may ways, legacy code is a more difficult target for a new microarchitecture. A mountain of x86 code has accumulated since the 1970s. Designing an engine to correctly run both legacy code and modern compiled code at world-class performance levels is like designing a new jet fighter to run on anything from jet-A fuel to whale blubber and coal. Bob Colwell, The Pentium Chronicles

31. CSE331 W02.31Irwin&Li 2006 PSU Review: MIPS Organization Processor Memory 32 bits 2 30 words read/write addr read data write data word address (binary) 0…0000 0…0100 0…1000 0…1100 1…1100 Register File src1 addr src2 addr dst addr write data 32 bits src1 data src2 data 32 registers ($zero - $ra) 32 5 5 5 ALU 32 0123 7654 byte address (big Endian)  Arithmetic instructions – to/from the register file  Load/store instructions - to/from memory

32. CSE331 W02.32Irwin&Li 2006 PSU Review: Unsigned Binary Representation HexBinaryDecimal 0x000000000…00000 0x000000010…00011 0x000000020…00102 0x000000030…00113 0x000000040…01004 0x000000050…01015 0x000000060…01106 0x000000070…01117 0x000000080…10008 0x000000090…10019 … 0xFFFFFFFC1…1100 0xFFFFFFFD1…1101 0xFFFFFFFE1…1110 0xFFFFFFFF1…1111 2 32 - 1 2 32 - 2 2 32 - 3 2 32 - 4 2 32 - 1 1 1 1... 1 1 1 1 bit 31 30 29... 3 2 1 0 bit position 2 31 2 30 2 29... 2 3 2 2 2 1 2 0 bit weight 1 0 0 0... 0 0 0 0 - 1

33. CSE331 W02.33Irwin&Li 2006 PSU Review: Signed Binary Representation 2’sc binarydecimal 1000-8 1001-7 1010-6 1011-5 1100-4 1101-3 1110-2 1111 00000 00011 00102 00113 01004 01015 01106 01117 2 3 - 1 = -(2 3 - 1) = -2 3 = 1010 complement all the bits 1011 and add a 1 complement all the bits 0101 and add a 1 0110

34. CSE331 W02.34Irwin&Li 2006 PSU  Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2 registers have numbers $t0=$8,$s1=$17,$s2=$18  Instruction Format: Can you guess what the field names stand for? Machine Language - Arithmetic Instruction op rs rt rd shamt funct 000000 10001 10010 01000 00000 100000

35. CSE331 W02.35Irwin&Li 2006 PSU  Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2 registers have numbers $t0=$8,$s1=$17,$s2=$18  Instruction Format: Can you guess what the field names stand for? Machine Language - Arithmetic Instruction op rs rt rd shamt funct 000000 10001 10010 01000 00000 100000

36. CSE331 W02.36Irwin&Li 2006 PSU MIPS Instruction Fields  op  rs  rt  rd  shamt  funct op rs rt rd shamt funct 6 bits5 bits 6 bits= 32 bits

37. CSE331 W02.37Irwin&Li 2006 PSU MIPS Instruction Fields  op  rs  rt  rd  shamt  funct op rs rt rd shamt funct 6 bits5 bits 6 bits= 32 bits opcode indicating operation to be performed address of the first register source operand address of the second register source operand the register destination address shift amoun t (for shift instructions) function code that selects the specific variant of the operation specified in the opcode field

38. CSE331 W02.38Irwin&Li 2006 PSU  Consider the load-word and store-word instr’s l What would the regularity principle have us do? -But... Good design demands compromise  Introduce a new type of instruction format l I-type for data transfer instructions (previous format was R-type for register)  Example: lw $t0, 24($s2) Where's the compromise? Machine Language - Load Instruction op rs rt 16 bit number 23 hex 18 8 24 100011 10010 01000 0000000000011000

39. CSE331 W02.39Irwin&Li 2006 PSU  Consider the load-word and store-word instr’s l What would the regularity principle have us do? -But... Good design demands compromise  Introduce a new type of instruction format l I-type for data transfer instructions (previous format was R-type for register)  Example: lw $t0, 24($s2) Where's the compromise? Machine Language - Load Instruction op rs rt 16 bit number 23 hex 18 8 24 100011 10010 01000 0000000000011000

40. CSE331 W02.40Irwin&Li 2006 PSU Memory Address Location  Example: lw $t0, 24($s2) Memory dataword address (hex) 0x00000000 0x00000004 0x00000008 0x0000000c 0xf f f f f f f f $s2 0x12004094 0x00000002 24 10 + $s2 = Note that the offset can be positive or negative

41. CSE331 W02.41Irwin&Li 2006 PSU Memory Address Location  Example: lw $t0, 24($s2) Memory dataword address (hex) 0x00000000 0x00000004 0x00000008 0x0000000c 0xf f f f f f f f $s2 0x12004094 0x00000002 24 10 + $s2 = Note that the offset can be positive or negative... 1001 0100 +... 0001 1000... 1010 1100 = 0x120040ac $t0

42. CSE331 W02.42Irwin&Li 2006 PSU  Example: sw $t0, 24($s2)  A 16-bit offset means access is limited to memory locations within a range of  2 13 = 8,192 words (  2 15 = 32,768 bytes) of the address in the base register $s2 l 2’s complement (1 sign bit + 15 magnitude bits) Machine Language - Store Instruction op rs rt 16 bit number 43 18 8 24 101011 10010 01000 0000000000011000

43. CSE331 W02.43Irwin&Li 2006 PSU  Example: sw $t0, 24($s2)  A 16-bit offset means access is limited to memory locations within a range of +2 13 -1 to -2 13 (~8,192) words (+2 15 -1 to -2 15 (~32,768) bytes) of the address in the base register $s2 l 2’s complement (1 sign bit + 15 magnitude bits) Machine Language - Store Instruction op rs rt 16 bit number 43 18 8 24 101011 10010 01000 0000000000011000

44. CSE331 W02.44Irwin&Li 2006 PSU  What instruction format is used for the addi ? addi$s3, $s3, 4#$s3 = $s3 + 4  Machine format: Machine Language – Immediate Instructions

45. CSE331 W02.45Irwin&Li 2006 PSU  What instruction format is used for the addi ? addi$s3, $s3, 4#$s3 = $s3 + 4  Machine format: Machine Language – Immediate Instructions op rs rt 16 bit immediate I format 8 19 19 4  The constant is kept inside the instruction itself! l So must use the I format – Immediate format l Limits immediate values to the range +2 15 –1 to -2 15

46. CSE331 W02.46Irwin&Li 2006 PSU Instruction Format Encoding  Can reduce the complexity with multiple formats by keeping them as similar as possible l First three fields are the same in R-type and I-type  Each format has a distinct set of values in the op field InstrFrmtoprsrtrdshamtfunctaddress add R0reg 032 ten NA sub R0reg 034 ten NA addi I8 ten reg NA constant lw I35 ten reg NA address sw I43 ten reg NA address

47. CSE331 W02.47Irwin&Li 2006 PSU Assembling Code  Remember the assembler code we compiled last lecture for the C statement A[8] = A[2] - b lw$t0, 8($s3)#load A[2] into $t0 sub$t0, $t0, $s2#subtract b from A[2] sw$t0, 32($s3)#store result in A[8]  Assemble the MIPS object code for these three instructions (decimal is fine) lw sw sub

48. CSE331 W02.48Irwin&Li 2006 PSU Assembling Code  Remember the assembler code we compiled last lecture for the C statement A[8] = A[2] - b lw$t0, 8($s3)#load A[2] into $t0 sub$t0, $t0, $s2#subtract b from A[2] sw$t0, 32($s3)#store result in A[8]  Assemble the MIPS object code for these three instructions (decimal is fine) 35 lw 198843 sw 198320 sub 8188034

49. CSE331 W02.49Irwin&Li 2006 PSU Review: MIPS Instructions, so far CategoryInstrOp Code ExampleMeaning Arithmetic (R format) add0 & 32 add $s1, $s2, $s3$s1 = $s2 + $s3 subtract0 & 34 sub $s1, $s2, $s3$s1 = $s2 - $s3 Arithmetic (I format) add immediate 8addi $s1, $s2, 4$s1 = $s2 + 4 Data transfer (I format) load word35lw $s1, 100($s2)$s1 = Memory($s2+100) store word43sw $s1, 100($s2)Memory($s2+100) = $s1

50. CSE331 W02.50Irwin&Li 2006 PSU Two Key Principles of Machine Design 1. Instructions are represented as numbers 2. Programs are stored in memory to be read or written, just like numbers  Stored-program concept l Programs can be shipped as files of binary numbers – binary compatibility l Computers can inherit ready- made software provided they are compatible with an existing ISA – leads industry to align around a small number of ISAs Accounting prg (machine code) C compiler (machine code) Payroll data Source code in C for Acct prg Memory

51. CSE331 W02.51Irwin&Li 2006 PSU Review: MIPS R3000 ISA  Instruction Categories l Load/Store l Computational l Jump and Branch l Floating Point -coprocessor l Memory Management l Special  3 Instruction Formats: all 32 bits wide R0 - R31 PC HI LO OPrs rt rdshamtfunct OPrs rt 16 bit number OP 26 bit jump target Registers R format I format 6 bits5 bits 6 bits