1. Steven Koelmeyer BDS(hons)1 Reconfigurable Hardware for use in Ad Hoc Sensor Networks Supervisors Charles Greif Nandita Bhattacharjee

2. Steven Koelmeyer BDS(hons) 2 Introduction Overview Project Aim Ad Hoc sensor motes What was Achieved

3. Steven Koelmeyer BDS(hons) 3 Overview The Smart Dust Project was started at Berkeley University sponsored by DARPA The aim was to create the smallest possible Ad-Hoc sensor nodes Small enough that releasing thousands into an environment would be insignificant

4. Steven Koelmeyer BDS(hons) 4 Duck Island Over 190 nodes including temperature, humidity, barometric pressure, infra-red and cameras

5. Steven Koelmeyer BDS(hons) 5 Overview Current Technology allows for extremely small wireless devices Capable of basic packet transmission, limited processing ability and taking sensor samples

6. Steven Koelmeyer BDS(hons) 6 Sensor Motes: Structure

7. Steven Koelmeyer BDS(hons) 7 Sensor Motes: Structure The CPU is an Atmel ATmega128 RISC architecture, internal SRAM, Flash memory and EEPROM, internal analogue to digital converter

8. Steven Koelmeyer BDS(hons) 8 Sensor Motes: Software Nodes each run an embedded Operating System called TinyOS Applications are written in NesC Tools and Utilities are java based

9. Steven Koelmeyer BDS(hons) 9 Limitations Limiting factors  Power Storage  Processor size  Communication Range Reconfigurable hardware offers increased processing ability without severely impacting on power

10. Steven Koelmeyer BDS(hons) 10 Reconfigurable Hardware Reconfigurable hardware comes in the form of:  Programmable Logic Devices (PLDs)  Complex PLDs  Field Programmable Gate Arrays (FPGAs) FPGAs being the choice for this project

11. Steven Koelmeyer BDS(hons) 11 FPGA Performance Reconfigurable hardware allows for the flexibility of Microprocessors while providing the speed of an Application Specific Integrated Circuit

12. Steven Koelmeyer BDS(hons) 12 The Reconfigurable Hardware Field Programmable Gate Array (FPGA) Programmed with VHDL After being compiled you end up with a bitstream entity BUFFERx8 is port ( in1: in STD_LOGIC; out1: out STD_LOGIC); end bufferx8; architecture STRUCTURE of BUFFERx8 is begin buf1 : process (in1) begin if ( in1 = '1' ) then out1 <= '1'; else out1 <= '0'; end if; end process; end STRUCTURE;

13. Steven Koelmeyer BDS(hons) 13 Bit stream format Xilinx ASCII Bitstream Created by Bitstream D.27 Design name: statemachine_5_out.ncd Architecture:spartan2 Part: 2s200pq208 Date: Tue Sep 28 13:58:32 2004 Bits: 1335840 11111111111111111111111111111111 10101010100110010101010101100110 00110000000000001000000000000001 00000000000000000000000000000111 00110000000000010110000000000001 00000000000000000000000000010001 00110000000000010010000000000001 00000000100000000011111100101101 00110000000000001100000000000001 00000000000000000000000000000000 00110000000000001000000000000001

14. Steven Koelmeyer BDS(hons) 14 Boundary Scan Boundary Scan was originally developed by the Joint Test Action Group (JTAG) for in- circuit testing of complex logic Replace “Bed of Nails” on single layer circuits Serial interface using instructions for different operations JTAG is controlled on devices through a Test Access Port

15. Steven Koelmeyer BDS(hons) 15 Example Instruction Set

16. Steven Koelmeyer BDS(hons) 16 TAP Controller

17. Steven Koelmeyer BDS(hons) 17 Testing Initial testing was done using a newer Spartan 2 XS200 digilab board

18. Steven Koelmeyer BDS(hons) 18 Design and Development

19. Steven Koelmeyer BDS(hons) 19 Simulation Simulation can be performed by compiling the TinyOS code for PC instead of sensor motes Can be run in real time Also able to use file I/O functions FPGA was attached to the parallel port

20. Steven Koelmeyer BDS(hons) 20 Simulation Before downloading the bit stream the FPGA must be reset A specific pattern of signals into the chip must be followed down to hundreds of nanoseconds.

21. Steven Koelmeyer BDS(hons) 21 Simulation A bit stream download in simulation takes 3 minutes Does not wait for transmissions No errors or retransmissions Runs at computers CPU speed

22. Steven Koelmeyer BDS(hons) 22 Implementation FPGA is mounted onto a circuit board Sit on top as a daughter board

23. Steven Koelmeyer BDS(hons) 23 Implementation Bit stream is downloaded to the Base Station and broadcast over the wireless link

24. Steven Koelmeyer BDS(hons) 24 Applications Image analysis  Car Number Plates  Data Compression  Face Recognition

25. Steven Koelmeyer BDS(hons) 25 Insert demonstration here