1. Cost-Oriented Design of a 14-bit Current Steering DAC Macrocell Ohio University School of Electrical Engineering and Computer Science May 25-28 th, 2003 IEEE International Symposium on Circuits and Systems Russell P. Mohn Sarnoff Corporation Janusz A. Starzyk Ohio University

2. May 25-28 th, 2003 Outline Introduction Statistical Yield Model Reduction of Systematic Errors Design Cost Consideration DAC Implementation Conclusion and Future Work

3. May 25-28 th, 2003 Introduction  Design Consideration based On the Statistical Model  Current Source Analysis  Reference Circuit Design and Analysis  Spreading of the Composite Transistors and Random Walk  Thermometer Circuit Design  Glitches and Dynamic Performance  Architectures and Layout  Top Level Simulation Results  Estimated Design Performance

4. May 25-28 th, 2003 Organization The DNL and INL Specifications Design Consideration based On the Statistical Model Segmentation of the Composite Transistors and Random Walk Glitches and Dynamic Performance Architectures and Layout Simulation Results Summary and Estimated Design Performance Figures

5. May 25-28 th, 2003 INL yield vs. relative current- source matching

6. May 25-28 th, 2003 DNL standard deviation for the segmented architecture B=4, so to meet the requirements for DNL

7. May 25-28 th, 2003 Segmentation of the Composite Transistors and Random Walk depends on the transistor area A and spacing D as where A , A VT and S  are process related constants

8. May 25-28 th, 2003 Mismatch parameters as reported for various processes

9. May 25-28 th, 2003 Segmentation of the Composite Transistors and Random Walk The random errors are determined by mismatch The systematic errors are determined by process, temperature, and electrical gradients In optimally designed DAC the INL and DNL errors depend only on the random errors level Increasing transistor area reduces the random errors. The systematic errors are layout-dependent and are minimized by transistor switching scheme.

10. May 25-28 th, 2003 Random errors - unit transistor requirements The minimum area of the unit transistor Parameters A  and A VT are technology dependent

11. May 25-28 th, 2003 The Level of Systematic Errors where k=A cell /A>1 is a current cell layout coefficient with A cell -unit current cell area

12. May 25-28 th, 2003 Current-source Matching vs. the Design Area for 12 bit DAC Green line indicates the effect of systematic errors

13. May 25-28 th, 2003 Basic Current Source

14. May 25-28 th, 2003 Current Source Analysis uneven output voltage Iout1=13.33mA, Iout2=0 mA, Vout1=1V, Vout2=0 V

15. May 25-28 th, 2003 Current Source Analysis uneven output voltage Vout2 Vout1 Io Vd src Vd c Ioff dI In order to achieve satisfactory INL level we must keep the cut-off current low So the cut-off current is limited by

16. May 25-28 th, 2003 Current Source Analysis even output voltage Iout1=Iout2=6.66 mA, Vout1=Vout2=0.5V

17. May 25-28 th, 2003 Reference Resistor and Output Current The following empirical relation holds for Iout<20mA

18. May 25-28 th, 2003 Reference Resistor and Output Current

19. May 25-28 th, 2003 Layout specifications of the 12-bit DAC DAC is built as a segmented architecture with 8-bit thermometer and 4-bit binary sections (to lower the glitches) LSB cell area (1/4 of unary source cell) is A=308  m 2 with W=17  m and L=18  m 8-bit thermometer decoder is designed in two groups- one with 3 thermometer bits and second with 5 bits (MSBs) Random walk is implemented with derived permutation sequence to minimize systematic errors Symmetrical layout, synchronization of control signals, synchronization of unary and binary current source transistor switching, and the cascode structure of the unit current sources control dynamic performance.

20. May 25-28 th, 2003 Spreading of the Composite Transistors and Random Walk The random errors are determined by mismatch The systematic errors are determined by process, temperature, and electrical gradients In optimally designed DAC the INL and DNL errors depend only on the random errors level Increasing transistor area reduces the random errors. The systematic errors are layout-dependent and are minimized by transistor switching scheme.

21. May 25-28 th, 2003 Reduction of Linear Systematic Errors To compensate for linear errors a symmetrical splitting is required Each transistor will be split into 4 locations

22. May 25-28 th, 2003 Spreading and random walk comparison

23. May 25-28 th, 2003 Permutation array

24. May 25-28 th, 2003 Wiring over the current source array

25. May 25-28 th, 2003

26. Wiring - via Placement in Current Sources Current sources are connected to horizontal wires sequentially

27. May 25-28 th, 2003 Wiring - Latch to Current Source Connection

28. May 25-28 th, 2003 Wiring - programmable via placement

29. May 25-28 th, 2003 Programmable via placement second quadrant

30. May 25-28 th, 2003 Layout Signal S2(32) Large capacitive load Connects 4 symmetrically spread current sources Unary current source 256 turned OFF

31. May 25-28 th, 2003 Layout Signals S2(32) and S2(33) Current sources controlled by S2(33) are far away from those controlled by S2(32) Switching sequence designed to minimize systematic errors

32. May 25-28 th, 2003 Layout Signals S2(32), S2(33), and S2(34)

33. May 25-28 th, 2003 Glitches The glitch current where A gl is the glitch amplitude, t gl is the glitch period, and t 0 is the synchronization mismatch (delay time)

34. May 25-28 th, 2003 Dynamic Performance For dynamic performance of DAC due to glitches and parasitic effects the following are recommended : jsynchronize the control signals of the switching transistors; jreduce the voltage fluctuation on the drains of the current sources during switching jcarefully switch the current source transistor on/off jreduce coupling of the control signals through lowering the voltage of the power supply of the latches. jincrease the output resistance in high frequency applications

35. May 25-28 th, 2003 Dynamic Performance The synchronization is achieved by equalizing each latch output load capacitance. Using a large channel length unit current source transistor and tuning the crossing point of the switching control signals such that both switches are never switched off at the same time solves voltage fluctuation at the drain problem Using an additional cascode transistor increases output impedance for high frequency applications –This architecture has an additional advantage of lowering glitch energy due to the drain voltage variations of the unit source.

36. May 25-28 th, 2003 Layout 1 column (8 rows) of latches Vertical green wires: Latch input from D flip- flops Latch output to current source array Equal load

37. May 25-28 th, 2003 Simulated Test Conditions

38. May 25-28 th, 2003 Binary Driven LSB Current Sources

39. May 25-28 th, 2003 Layout Equalizing capacitive load between binary latches and unary latches Load determined by total length of wires to unary current sources Binary wire Unary wire

40. May 25-28 th, 2003 DNL and INL for Unbalanced Load

41. May 25-28 th, 2003 Equalizing the Binary/Unary Latch Loads

42. May 25-28 th, 2003 Digital Sine Excitations

43. May 25-28 th, 2003 Sine Output

44. May 25-28 th, 2003 Single tone output spectrum unmatched latch load

45. May 25-28 th, 2003 DNL and INL for Balanced Load Condition 2

46. May 25-28 th, 2003 DNL and INL for Balanced Load Condition 1

47. May 25-28 th, 2003 DNL and INL for Balanced Load Condition 3

48. May 25-28 th, 2003 2^12 Ramp

49. May 25-28 th, 2003 2^12 Ramp INL & DNL Unbalanced capacitive unary and binary loads INL(2^12) < 10*INL(2^7) 17 days simulation versus 8 hours simulation

50. May 25-28 th, 2003 DNL and INL for Balanced Load Condition 1 - Vout 1.5V

51. May 25-28 th, 2003 DNL and INL for Balanced Load Condition 3 - Vout 1.5V

52. May 25-28 th, 2003 Single tone output spectrum matched latch load

53. May 25-28 th, 2003 Single tone output spectrum: Closer Look

54. May 25-28 th, 2003 Terayon Load Analysis (HPADS) 10 MHz signal 10nA (left) 10mA (right)

55. May 25-28 th, 2003 Output of Terayon post-D/A Filter Differential Output

56. May 25-28 th, 2003 Output of Terayon post-D/A Filter Cutoff around 80 MHz Limited Resolution

57. May 25-28 th, 2003 DC Offset Simulation

58. May 25-28 th, 2003 Power Supply Rejection - AC Analysis

59. May 25-28 th, 2003 Power Supply Rejection - AC Analysis Finally the PSRR depends only on the design voltages Using the design values Which agrees with the simulation results

60. May 25-28 th, 2003 Digital inputs along top Analog inputs/outputs along bottom 1716.5µm x 1700.0 µm Area = 2.918mm 2 Analog circuitry separated from noisy digital environment Two guard rings 40 µm n-well 100 µm p+ Full view of the D/A Noisy digital Semi-quiet digital Quiet analog

61. May 25-28 th, 2003 Symmetries about orthogonal axes: Binary Current Sources Unary Current Sources Modular design in both digital and analog sections Digital inputs have at least 4.46 µm separation Reference circuit tightly integrated with sensitive analog circuitry Full view of the D/ A

62. May 25-28 th, 2003 8 Binary inputs DAC_D(4)... DAC_D(11) encoded in thermometer code D Flip-flop organization 8 rows x 32 columns DAC_D(4)... DAC_D(6) select 1 of 8 rows DAC_D(7)... DAC_D(11) select 1 of 32 columns Column select Distributed logic minimizes space Local clock drivers Layout

63. May 25-28 th, 2003 Layout Distributed thermometer encoder D flip-flops above latches In black 1 row select 1 column select at C(i) and C(i+1)

64. May 25-28 th, 2003 Layout 1 Column (8 rows) of D flip-flops 8 complementary signals carried on vertical green wires local clock driver, column decode logic

65. May 25-28 th, 2003 Layout Clock distribution Inverted clk signal to digital input flip-flops clk signal split left/right from center

66. May 25-28 th, 2003 Layout Vertical green wires: Routing from D flip- flops to latches Routing from latches to current source array

67. May 25-28 th, 2003 Layout Wiring over current source array Comp. signals: S1, S2 32 x 32 wires per quarter unary source Shield in met2, met 5 Horizontal in met3 Vertical in met4 Wire width = 0.22 µm Wire spacing = 1.0 µm

68. May 25-28 th, 2003 Salient DAC Specifications Resolution: 12 bits Conversion Rate: 180 MSPS Differential current outputs 20mA at full scale Gain Error: ±10% of full scale DNL: ±1 LSB INL: ±2 LSB Wideband SFDR 1MHz out: 70dBc, … 80MHz out: 50dBc Narrowband SFDR 1MHz out (within ±100 kHz window): 80dBc Max Power: 200mWPower Down:15uA Trise, Tfall (Cl<10pF, Rl=50): 1.6-2.5ns Trise-Tfall: 0.1-0.2 ns Glitch Energy Error: 2.0-5.0 pV-s