1. [M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Oct. 29 Overall Project Objective : Dynamic Control The Traffic Lights

2. Status  Design Proposal  Chip Architecture  Behavioral Verilog Implementation  Size estimates  Floorplanning  Behavioral Verilog simulated  Gate Level Design  Component Layout/Simulation  Chip Layout  Complete Simulation

3. Data Input Initial Values Clock Operation T, Left-Turn Counter R, r, R_ L, r_ l Flow Control FSM Light Contro l FSM Selection

4. Current Version Wire routing on each block

5. ALU Update  Progress  Row of Full Adder- in progress  Array Multiplier  VDD + GND lines connected with M3  Issue: Connecting from one row to another  Solutions  Use Wire Jumping? Bad idea  Use Metal 4? Not as of a Bad idea  Would only be used as an interconnect between rows as all outputs can either be M2  New Mirror Adder to complement other mirror adder?  Good idea and a work in progress  Requires M3 to work as an interconnect between rows asides from just inputs

6. Full Adder Row(10x2)

7. Something to Consider  Area of Array Multiplier  Given 10x10 um^2 Full Adder. Array will be ~110x100 um^2  If I use 5 FAs at 10x10 um^2 and 5 FAs at ~10x6 um^2  ~85x100 um^2 for the New Total Area  Will achieve the 110x100 um^2 first since it ’ s a work in progress already  Will update to 85x100 um^2 if time allows

8. Mirror Adder V1

9. Mirror Adder V2(small)

10. Flow Control FSM

11. Layout for Light Control FSM  Build preliminary layouts by using standard cells and then flatten them to do optimization.  The problem about sharing substrate contacts is fixed.  Try to make routings passing above transistors as possible.

12. FSM decoder Layout for decoder is finished. The area is smaller than previous version. M3: vertical, M2:horizontal. DRC & LVS clean.

13. FSM Output Preliminary version for this block DRC & LVS clean.

14. FSM Encoder Preliminary version for this block DRC & LVS clean.

15. FSM Comparator Preliminary layout version1. May need to switch the M2 and M3 in this layout to be coherent with other blocks.

16. FSM Comparator Preliminary layout version2. Need to switch the M2 and M3 as well. Not quite sure which one is better, but this one seems to be easier to do routing.

17. FSM Next State Still can’t find a way to fit all wires above these transistors. May need to waste extra space for routing. ?

18. DFF-Register New Size = 14.4 x 6.48

19. 2:1 MUX New Size = 4.68 x 6.48

20. 11 Reg. New Size = 14.4 x 65.34 Local Metal : M1 M2 Global : M3 or M4 (only one) Share three inverters to create CLK_BAR

21. 8:1 MUX Local Metal : M1 M2 Global : M3 or M4 (only one) Size : 8.28 x 23.58

22. 16:1 MUX Local Metal : M1 M2 Global : M3 Size : 8.28 x 46.26

23. Register (1bit) 2X1 MUX 16.6 6.6 13.5 6.5 Ex-Floor Plan :New Floor Plan : I will update this week Register (1bit) 2X1 MUX (without keeper) 14.4 6.48 4.6 6.48 Data

24. Some other layout  DEMUX + Shift Register  Different bits Register  Many other kinds of MUX  After new floorplan, other shape of registers.  Comparator  Increment  More and More … Hope I could finish by Monday

25. Question ?