1. 08/31/2001Copyright CECS & The Spark Project Center for Embedded Computer Systems University of California, Irvine http://www.cecs.uci.edu/~spark Conditional Speculation and its Effects on Performance and Area for High-Level Synthesis Sumit GuptaNikil Dutt Nick Savoiu Rajesh Gupta Alex Nicolau SPARK High Level Synthesis System Supported by Semiconductor Research Corporation

2. 2 Copyright CECS & The Spark Project High Level Synthesis From C to CDFG to Architecture

3. 3 Copyright CECS & The Spark Project Scheduling with Given Resource Allocation Resource Constraints +<

4. 4 Copyright CECS & The Spark Project Conditional Speculation ++ - < Resource Constraints +< Conditionally Speculate Unused/idle resource slots

5. 5 Copyright CECS & The Spark Project Conditional Speculation ++- < Resource Constraints +< -  Higher resource utilization inside conditionals  Shorter schedule lengths

6. 6 Copyright CECS & The Spark Project Creation of idle slots by Speculation -+ - < BB 1BB 2 BB 3 BB 0 xy aa z Speculate

7. 7 Copyright CECS & The Spark Project After Speculation -+ - < BB 1BB 2 BB 3 BB 0 xy aa z a = ba = c bc Conditionally Speculate

8. 8 Copyright CECS & The Spark Project After Conditional Speculation -+< BB 1BB 2 BB 3 BB 0 xy a = ba = c b c -- b c z1 z2

9. 9 Copyright CECS & The Spark Project Generalized Code Motions + + + If Node TF Conditional Speculation Reverse Speculation Speculation Across Hierarchical Blocks

10. 10 Copyright CECS & The Spark Project Recent Related Work  Code motions in the presence of conditionals u Condition Vector List Scheduling [Wakabayashi 89] u Symbolic Scheduling [Radivojevic 96] u WaveSched Scheduler [Lakshminarayana 98] u Basic Block Control Graph Scheduling [Santos 99]  Limitations u Arbitrary nesting of conditionals and loops not handled or handled poorly u Ad hoc optimizations F Not part of a complete synthesis system u Limited analysis of logic and control costs

11. 11 Copyright CECS & The Spark Project The Spark High-Level Synthesis Methodology  Developed a set of speculative code motions along with supporting transformations  Implemented in a comprehensive synthesis framework u Input: Behavioral description in ANSI-C u Output: Synthesizable register-transfer level VHDL  Quality of results measured in terms of u Scheduling results: cycles in longest path u Controller size: number of states in FSM u Logic synthesis results: critical path length,unit area

12. 12 Copyright CECS & The Spark Project The Spark High-Level Synthesis Framework  Experiments performed using two benchmarks:  ADPCM Encode and MPEG-1 Prediction Block

13. 13 Copyright CECS & The Spark Project Improvements of up to 50 % in Number of States in FSM and Cycles on Longest Path due to Code Motions Within Basic Blocks Within BBs, Across Hierarchical Blocks Within BBs, Across Hier Blocks, Speculation Within BBs, Across Hier Blocks, Spec, Early Condition Execution Within BBs, Across Hier Blocks, Spec, Early Cond Exec, Conditional Speculation Allowed Code Motions Conditional Speculation: Leads to between 10 to 30 % Improvements

14. 14 Copyright CECS & The Spark Project Synthesis Results using Synopsys Design Compiler Within Basic Blocks Within BBs, Across Hierarchical Blocks, Speculation Within BBs, Across Hier Blocks, Spec, Early Condition Execution Within BBs, Across Hier Blocks, Spec, Early Cond Exec, Conditional Speculation Allowed Code Motions  Conditional Speculation leads to u Reduced circuit delays: between 7 to 35 % u Increased Area: between 4 to 8 % F Area figures are high in absolute terms

15. 15 Copyright CECS & The Spark Project Increasing sizes of steering logic and associated control logic  Code motions lead to u Higher Resource Sharing and Utilization u Larger Multiplexors u Larger Control Circuits Control Logic ALU ++

16. 16 Copyright CECS & The Spark Project Increasing sizes of steering logic and associated control logic Control Logic ALU +++  Code motions lead to u Higher Resource Sharing and Utilization u Larger Multiplexors u Larger Control Circuits

17. 17 Copyright CECS & The Spark Project Increasing sizes of steering logic and associated control logic Control Logic ALU ++++  Code motions lead to u Higher Resource Sharing and Utilization u Larger Multiplexors u Larger Control Circuits

18. 18 Copyright CECS & The Spark Project Interconnect minimization by resource binding  Minimize the complexity of steering logic u Multiplexors and demultiplexors  Bind operations with same inputs or outputs to same functional units  Bind variables, which are inputs/outputs to same functional units, to the same registers  Both of these binding problems have been formulated as network flow problems

19. 19 Copyright CECS & The Spark Project Reduction in Area by Interconnect Minimizing Resource Binding Critical Path Total Delay Unit Area Critical Path Total Delay Unit Area Naïve Resource Binding Interconnect Minimizing Resource Binding  Reductions in area of between 15-32 %  Fairly constant critical path lengths and circuit delay

20. 20 Copyright CECS & The Spark Project Conclusions  Synthesis results after code motions u Considerable gain in execution cycles and controller size u Large Area costs due to interconnect (multiplexors)  Interconnect minimizing resource binding leads to significant area reductions  Benchmarks used are large real-life applications Future Work:  Develop better cost models for code motions u Consider effects on interconnect while scheduling u Create a notion of global cost of the design

21. 21 Copyright CECS & The Spark Project Thank you ! Please do drop by during the Poster session

22. 08/31/2001Copyright CECS & The Spark Project Center for Embedded Computer Systems University of California, Irvine http://www.cecs.uci.edu/~spark Conditional Speculation and its Effects on Performance and Area for High-Level Synthesis Sumit GuptaNikil Dutt Nick Savoiu Rajesh Gupta Alex Nicolau SPARK High Level Synthesis System Supported by Semiconductor Research Corporation

23. 23 Copyright CECS & The Spark Project Additional Slides

24. 24 Copyright CECS & The Spark Project Reducing Interconnections by Improved Operation Binding 1:a=b+c ALU 1 2:d=e+f ALU 2 4:h=a+c 3:g=e+d b,d,hf,a,g c e 3:g=e+d; 4:h=a+c 1:a=b+c; 2:d=e+f

25. 25 Copyright CECS & The Spark Project Reduced Interconnections after Operation Binding 1:a=b+c ALU 1 2:d=e+f ALU 2 4:h=a+c 3:g=e+d b,d,gf,a,h c e

26. 26 Copyright CECS & The Spark Project Reducing Interconnections by Improved Variable Binding 1:a=b+c ALU 1 2:d=e+f ALU 2 4:h=a+c 3:g=e+d b,d,gf,a,h c e

27. 27 Copyright CECS & The Spark Project Reduced Interconnections due to Improved Resource Binding 1:a=b+c ALU 1 2:d=e+f ALU 2 4:h=a+c 3:g=e+d b,a,hf,d,g c e

28. 28 Copyright CECS & The Spark Project Improvements of up to 50 % in Number of States in FSM and Cycles on Longest Path due to Code Motions Within Basic Blocks Within BBs, Across Hierarchical Blocks Within BBs, Across Hier Blocks, Speculation Within BBs, Across Hier Blocks, Spec, Early Condition Execution Within BBs, Across Hier Blocks, Spec, Early Cond Exec, Conditional Speculation Allowed Code Motions

29. 29 Copyright CECS & The Spark Project Synthesis Results using Synopsys Design Compiler Within Basic Blocks Within BBs, Across Hierarchical Blocks, Speculation Within BBs, Across Hier Blocks, Spec, Early Condition Execution Within BBs, Across Hier Blocks, Spec, Early Cond Exec, Conditional Speculation Allowed Code Motions