Presentation is loading. Please wait.

Presentation is loading. Please wait.

Lecture 28 IEEE JTAG Boundary Scan Standard

Published by Modified over 9 years ago

Similar presentations

Presentation on theme: "Lecture 28 IEEE JTAG Boundary Scan Standard"— Presentation transcript:

1 Lecture 28 IEEE 1149.1 JTAG Boundary Scan Standard
Motivation Bed-of-nails tester System view of boundary scan hardware Elementary scan cell Test Access Port (TAP) controller Boundary scan instructions Summary Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

2 Motivation for Standard
Bed-of-nails printed circuit board tester gone We put components on both sides of PCB & replaced DIPs with flat packs to reduce inductance Nails would hit components Reduced spacing between PCB wires Nails would short the wires PCB Tester must be replaced with built-in test delivery system -- JTAG does that Need standard System Test Port and Bus Integrate components from different vendors Test bus identical for various components One chip has test hardware for other chips Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

3 Bed-of-Nails Tester Concept
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

4 Bed-of-Nails Tester Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 28

5 Purpose of Standard Lets test instructions and test data be serially fed into a component-under-test (CUT) Allows reading out of test results Allows RUNBIST command as an instruction Too many shifts to shift in external tests JTAG can operate at chip, PCB, & system levels Allows control of tri-state signals during testing Lets other chips collect responses from CUT Lets system interconnect be tested separately from components Lets components be tested separately from wires Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

6 System Test Logic Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 28

7 Instruction Register Loading with JTAG
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

8 System View of Interconnect
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

9 Boundary Scan Chain View
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

10 Elementary Boundary Scan Cell
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

11 Serial Board / MCM Scan Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 28

12 Parallel Board / MCM Scan
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

13 Independent Path Board / MCM Scan
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

14 Tap Controller Signals
Test Access Port (TAP) includes these signals: Test Clock Input (TCK) -- Clock for test logic Can run at different rate from system clock Test Mode Select (TMS) -- Switches system from functional to test mode Test Data Input (TDI) -- Accepts serial test data and instructions -- used to shift in vectors or one of many test instructions Test Data Output (TDO) -- Serially shifts out test results captured in boundary scan chain (or device ID or other internal registers) Test Reset (TRST) -- Optional asynchronous TAP controller reset Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

15 Tap Controller State Diagram
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

16 Tap Controller Timing Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 28

17 TAP Controller Power-Up Reset Logic
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

18 Boundary Scan Instructions
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

19 SAMPLE / PRELOAD Instruction -- SAMPLE
Purpose: Get snapshot of normal chip output signals Put data on bound. scan chain before next instr. Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

20 SAMPLE / PRELOAD Instruction -- PRELOAD
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

21 EXTEST Instruction Purpose: Test off-chip circuits and board-level interconnections Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

22 INTEST Instruction Purpose:
Shifts external test patterns onto component External tester shifts component responses out Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

23 INTEST Instruction Clocks
Control of applied system clock during INTEST Use of TCK for on-chip system logic clock Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

24 RUNBIST Instruction Purpose: Allows you to issue BIST command to component through JTAG hardware Optional instruction Lets test logic control state of output pins Can be determined by pin boundary scan cell Can be forced into high impedance state BIST result (success or failure) can be left in boundary scan cell or internal cell Shift out through boundary scan chain May leave chip pins in an indeterminate state (reset required before normal operation resumes) Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

25 CLAMP Instruction Purpose: Forces component output signals to be driven by boundary-scan register Bypasses the boundary scan chain by using the one-bit Bypass Register Optional instruction May have to add RESET hardware to control on-chip logic so that it does not get damaged (by shorting 0’s and 1’s onto an internal bus, etc.) Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

26 IDCODE Instruction Purpose: Connects the component device identification register serially between TDI and TDO In the Shift-DR TAP controller state Allows board-level test controller or external tester to read out component ID Required whenever a JEDEC identification register is included in the design Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

27 Device ID Register --JEDEC Code
Part Number (16 bits) Manufacturer Identity (11 bits) ‘1’ (1 bit) Version (4 bits) MSB LSB Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

28 USERCODE Instruction Purpose: Intended for user-programmable components (FPGA’s, EEPROMs, etc.) Allows external tester to determine user programming of component Selects the device identification register as serially connected between TDI and TDO User-programmable ID code loaded into device identification register On rising TCK edge Switches component test hardware to its system function Required when Device ID register included on user-programmable component Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

29 HIGHZ Instruction Purpose: Puts all component output pin signals into high-impedance state Control chip logic to avoid damage in this mode May have to reset component after HIGHZ runs Optional instruction Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

30 BYPASS Instruction Purpose: Bypasses scan chain with 1-bit register
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

31 Optional / Required Instructions
BYPASS CLAMP EXTEST HIGHZ IDCODE INTEST RUNBIST SAMPLE / PRELOAD USERCODE Status Mandatory Optional Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

32 Summary Boundary Scan Standard has become absolutely essential --
No longer possible to test printed circuit boards with bed-of-nails tester Not possible to test multi-chip modules at all without it Supports BIST, external testing with Automatic Test Equipment, and boundary scan chain reconfiguration as BIST pattern generator and response compacter Now getting widespread usage Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 28

Download ppt "Lecture 28 IEEE JTAG Boundary Scan Standard"

Similar presentations

Introduction to DFT Alexander Gnusin.

Introduction to DFT Alexander Gnusin.
Z. Stamenković 1, M. Giles 2, and F. Russi 2 1 IHP GmbH, Frankfurt (Oder), GERMANY 2 Synopsys Inc., Mountain View, CA, USA 13th IEEE European Test Symposium,

Z. Stamenković 1, M. Giles 2, and F. Russi 2 1 IHP GmbH, Frankfurt (Oder), GERMANY 2 Synopsys Inc., Mountain View, CA, USA 13th IEEE European Test Symposium,
BOUNDARY SCAN.

BOUNDARY SCAN.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt1 Lecture 31 System Test (Lecture 22alt in the Alternative Sequence) n Definition n Functional.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt1 Lecture 31 System Test (Lecture 22alt in the Alternative Sequence) n Definition n Functional.
Copyright 2001, Agrawal & BushnellLecture 12: DFT and Scan1 VLSI Testing Lecture 10: DFT and Scan n Definitions n Ad-hoc methods n Scan design  Design.

Copyright 2001, Agrawal & BushnellLecture 12: DFT and Scan1 VLSI Testing Lecture 10: DFT and Scan n Definitions n Ad-hoc methods n Scan design  Design.
FPGA Configuration. Introduction What is configuration? – Process for loading data into the FPGA Configuration Data Source Configuration Data Source FPGA.

FPGA Configuration. Introduction What is configuration? – Process for loading data into the FPGA Configuration Data Source Configuration Data Source FPGA.
Apr. 20, 2001VLSI Test: Bushnell-Agrawal/Lecture 311 Lecture 31 System Test n Definition n Functional test n Diagnostic test  Fault dictionary  Diagnostic.

Apr. 20, 2001VLSI Test: Bushnell-Agrawal/Lecture 311 Lecture 31 System Test n Definition n Functional test n Diagnostic test  Fault dictionary  Diagnostic.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 261 Lecture 26 Logic BIST Architectures n Motivation n Built-in Logic Block Observer (BILBO) n Test.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 261 Lecture 26 Logic BIST Architectures n Motivation n Built-in Logic Block Observer (BILBO) n Test.
LOGSYS Development Environment of Embedded Systems Tamás Raikovich Béla Fehér Péter Laczkó Budapest University of Technology and Economics Department of.

LOGSYS Development Environment of Embedded Systems Tamás Raikovich Béla Fehér Péter Laczkó Budapest University of Technology and Economics Department of.
Chip and Circuit Board Debugging Adam Hoover JTAG.

Chip and Circuit Board Debugging Adam Hoover JTAG.
FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR SRAM-based FPGA n SRAM-based LE –Registers in logic elements –LUT-based logic element.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR SRAM-based FPGA n SRAM-based LE –Registers in logic elements –LUT-based logic element.
Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt1 Lecture 21alt BIST -- Built-In Self-Test (Alternative to Lectures 25, 26 and 27) n Definition.

Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt1 Lecture 21alt BIST -- Built-In Self-Test (Alternative to Lectures 25, 26 and 27) n Definition.
Copyright 2001, Agrawal & BushnellDay-2 PM Lecture 101 Design for Testability Theory and Practice Lecture 10: DFT and Scan n Definitions n Ad-hoc methods.

Copyright 2001, Agrawal & BushnellDay-2 PM Lecture 101 Design for Testability Theory and Practice Lecture 10: DFT and Scan n Definitions n Ad-hoc methods.
ECE 331 – Digital System Design Flip-Flops and Registers (Lecture #18) The slides included herein were taken from the materials accompanying Fundamentals.

ECE 331 – Digital System Design Flip-Flops and Registers (Lecture #18) The slides included herein were taken from the materials accompanying Fundamentals.
JTAG Course Lecturer: Tomer Rothschild

JTAG Course Lecturer: Tomer Rothschild
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 301 Lecture 30 IEEE 1149.4 JTAG Analog Test Access Port and Standard n Motivation n Bus overview n.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 301 Lecture 30 IEEE JTAG Analog Test Access Port and Standard n Motivation n Bus overview n.
Liron Cohen 2006 1. 2 Introduction SVF was jointly developed by Texas Instruments and Teradyne in response to a need for the exchange of Boundary Scan.

Liron Cohen Introduction SVF was jointly developed by Texas Instruments and Teradyne in response to a need for the exchange of Boundary Scan.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 291 Lecture 29 IEEE 1149.1 JTAG Advanced Boundary Scan & Description Language (BSDL) n Special scan.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 291 Lecture 29 IEEE JTAG Advanced Boundary Scan & Description Language (BSDL) n Special scan.
Spring 08, Apr 17 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 System Test Vishwani D. Agrawal James J. Danaher.

Spring 08, Apr 17 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 System Test Vishwani D. Agrawal James J. Danaher.
1 Lecture 23 Design for Testability (DFT): Full-Scan n Definition n Ad-hoc methods n Scan design Design rules Scan register Scan flip-flops Scan test sequences.

1 Lecture 23 Design for Testability (DFT): Full-Scan n Definition n Ad-hoc methods n Scan design Design rules Scan register Scan flip-flops Scan test sequences.

Similar presentations

Ads by Google