1. Random Number Generator Dmitriy Solmonov W1-1 David Levitt W1-2 Jesse Guss W1-3 Sirisha Pillalamarri W1-4 Matt Russo W1-5 Design Manager – Thiago Hersan March 1, 2006 Component Layout and Floorplan Project Objective: Create a Cryptologically Secure Pseudo-Random Number Generator

2. Agenda Status Design Decisions Critical Layouts Power and Timing Analysis

3. Status Former C implementation Architecture Behavioral Design and Simulation Gate-Level Design and Simulation Preliminary Floorplan Schematic Design and Simulation Currently  Layout (15,800 of 33,225)  ~SRAM  Low 10 bits of the adder  D-Flip Flop  Some basic gates (as we need them) Awaiting Extraction, LVS, post-layout simulation

4. Design Decisions JKFF Need to be redesigned

5. JKFF Now using master-slave n-pass latches. 3 simple gates at input perform JK logic. Pros, cons

6. CS4_1, CS6 New Completed Layouts: 32-bit adder

7. CS4_1 Block

9. 3 Bit Add Block

11. SRAM New Layouts

12. Floorplan Schematic

13. Datapath

14. Putting it All Together (updated) W: 510uW R: 190uW 735ps8000um 2 17736 (M=10458 R=7278) SRAM 3.3 mW 38,400um 2 (3840um 2 ea.) 6400 (640 each) Registers(10 ) ~6.5mW500 MHz 151,900um 2 33225Total 575uW1.44ns25,200 um 2 (6300um 2 ea.) 5856 (1464 each) Adders (4x) PowerProp Delay AreaTransistor CountComponent 3 bit low 4 bits 138 132 594 71uW 100uW 298ns 397ns 200ps

15. Thanks! Any Questions?