1. Random Number Generator Dimtriy Solmonov W1-1 David Levitt W1-2 Jesse Guss W1-3 Sirisha Pillalamarri W1-4 Matt Russo W1-5 Design Manager- Thiago Hersan

2. Status Finished C implementation Architecture Verilog Datapath design In Process…  Simulation  Gate-Level Design  Preliminary Floorplan Unfinished Schematic Layout Extraction, LVS, post-layout simulation

3. Design Decisions Alpha 8 2 sets of 32 x 32 SRAM One dual bus SRAM Main adder unit chosen

4. Pipeline – Version 5.1 2 Stages 5 clock cycles (ticks) per stage. Not all registers update on the same tick value Assumptions –32-bit addition in two ticks –SRAM read in half a tick

5. Random Numbers  With original seed of all 1’s: –AA38AF8A8F2361738A122CBF4511461C16055A026C10217 64FD9254F66608094E6713B5D9A144E7F7385D61A5B443B 0824C6B5AE5BB18535C0A09FE6329950D1DDA642BB0763 2F26A872E048E203327C1F55BC126A8A2B814D5F1E23CB 71565F8957301760242573DAF0A1E41C9E89DC7DCEF91F E25B7F55B1419A49129EF5 –81B1CC28F282CD1C80749611EADE85E278B3DE0519C65 9435418F4C24399F7014A1505974E2AF4974C45AC92BED C8D3B07FB4E7F60D81C86C0715742A600BE0152B4E6D4 DF2A93B5075B5B1AA8CF406F5EAE2589287D9DAF745C1 05989132A98A858028026431FFE94E5C224890BCA1E3CF2 8F6C56A247C2912A8BBCD79AF

6. Project Main Blocks

7. Main DataPath

8. Stage 1 Receive I, I_prev. ------------------------------------------------------------------ 0) M1=M[i+32] | A1=(A >13) ------------------------------------------------------------------ 1) X=M[i]| A=A1+M1 ------------------------------------------------------------------ NOTE: Y get's updated at start of this tick 2) M3=M[X]| A=A1+M1| C1=(X==i-1) ------------------------------------------------------------------ 3) Y1=A+ (C1) ? Y : M3 ------------------------------------------------------------------ 4) Y1 = A + M3 ------------------------------------------------------------------

9. Stage 1

10. Stage 2 Receive B, Y1, X, I. ---------------------------------------------------------------------- 0) Y=B+Y1| YL=B[13:0]+Y1[13:0] ---------------------------------------------------------------------- 1) Y=B+Y1| M4=M[Y[13:8]] | C2=(I==Y[13:8]) ---------------------------------------------------------------------- 2) B = X+(C2) ? Y : M4 ---------------------------------------------------------------------- 3) B = X+(C2) ? Y : M4| M[i]=Y ---------------------------------------------------------------------- 4) R[i] = B ----------------------------------------------------------------------

11. Stage 2

12. Other optimizations Memory and registers updated at different edges of clock. One special adder