1. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 11 Design for Testability Theory and Practice January 15 – 17, 2005 Vishwani D. Agrawal James J. Danaher Professor Auburn University, AL 36849, USA vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal C. P. Ravikumar Texas Instruments Bnagalore, India revikumar@ti.com

2. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 12 Design for Testability Theory and Practice Lecture 1: Introduction n VLSI realization process n Verification and test n Ideal and real tests n Costs of testing n Roles of testing n A modern VLSI device - system-on-a-chip n Three-day course outline

3. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 13 VLSI Realization Process Determine requirements Write specifications Design synthesis and Verification Fabrication Manufacturing test Chips to customer Customer’s need Test development

4. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 14 Definitions n Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. n Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. n Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.

5. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 15 Verification vs. Test Verification n Verifies correctness of design. n Performed by simulation, hardware emulation, or formal methods. n Performed once prior to manufacturing. n Responsible for quality of design. Test n Verifies correctness of manufactured hardware. n Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware n Test application performed on every manufactured device. n Responsible for quality of devices.

6. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 16 Problems of Ideal Tests n Ideal tests detect all defects produced in the manufacturing process. n Ideal tests pass all functionally good devices. n Very large numbers and varieties of possible defects need to be tested. n Difficult to generate tests for some real defects. Defect-oriented testing is an open problem.

7. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 17 Real Tests n Based on analyzable fault models, which may not map on real defects. n Incomplete coverage of modeled faults due to high complexity. n Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. n Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.

8. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 18 Testing as Filter Process Fabricated chips Good chips Defective chips Prob(good) = y Prob(bad) = 1- y Prob(pass test) = high Prob(fail test) = high Prob(fail test) = low Prob(pass test) = low Mostly good chips Mostly bad chips Tested chips

9. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 19 Costs of Testing n Design for testability (DFT) Chip area overhead and yield reduction Performance overhead n Software processes of test Test generation and fault simulation Test programming and debugging n Manufacturing test Automatic test equipment (ATE) capital cost Test center operational cost

10. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 110 Present and Future* Transistors/sq. cm4 - 10M18 - 39M Pin count100 – 900160 - 1475 Clock rate (MHz)200 – 730530 - 1100 Power (Watts)1.2 – 612 - 96 Feature size (micron)0.25 - 0.150.13 - 0.10 1997 -2001 2003 - 2006 * SIA Roadmap, IEEE Spectrum, July 1999

11. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 111 Design for Testability (DFT) DFT refers to hardware design styles or added hardware that reduces test generation complexity. Motivation: Test generation complexity increases exponentially with the size of the circuit. Logic block A Logic block B Primary inputs (PI) Primary outputs (PO) Test input Test output Int. bus Example: Test hardware applies tests to blocks A and B and to internal bus; avoids test generation for combined A and B blocks.

12. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 112 Cost of Manufacturing Testing in 2000AD n 0.5-1.0GHz; analog instruments; 1,024 digital pins: ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272M n Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year n Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second

13. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 113 Roles of Testing n Detection: Determination whether or not the device under test (DUT) has some fault. n Diagnosis: Identification of a specific fault that is present on DUT. n Device characterization: Determination and correction of errors in design and/or test procedure. n Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.

14. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 114 A Modern VLSI Device System-on-a-chip (SOC) DSP core RAM ROM Inter- face logic Mixed- signal Codec Data terminal Transmission medium

15. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 115 Course Outline Part I: Introduction n Basic concepts and definitions n Yield and product quality n Fault modeling n Day 1 AM n Reference, Chapters 1 – 4: M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000. http://www.eng.auburn.edu/~vagrawal/BOOK/books.html

16. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 116 Course Outline (Cont.) Part II: Test Methods n Logic and fault simulation n Testability measures n Combinational circuit ATPG n Sequential circuit ATPG n Memory test n Analog test n Day 1 PM and Day 2 AM n Reference, Chapters 5 – 11: M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000. http://www.eng.auburn.edu/~vagrawal/BOOK/books.html

17. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 117 Course Outline (Cont.) Part III: DFT n Scan design n Built-in self-test (BIST) n Boundary scan and analog test bus n System diagnosis and core-based design n Day 2 PM n Reference, Chapters 14 – 18: M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000. http://www.eng.auburn.edu/~vagrawal/BOOK/books.html

18. Copyright 2001, Agrawal & BushnellDay-1 AM Lecture 118 Course Outline (Cont.) Part IV: Advanced DFT n Test compression techniques n At-speed testing techniques for SoC n Signal integrity issues in test n Power issues in test n Day 3 – AM and PM